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A parallel bus self-test method and system

A self-checking system and bus technology, applied in error detection/correction, instruments, electrical digital data processing, etc., can solve problems such as bus failures and device malfunctions, and achieve the effect of avoiding system data errors

Active Publication Date: 2018-03-16
XUJI GRP +3
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  • Description
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Problems solved by technology

[0003] The purpose of the present invention is to provide a parallel bus self-test method and system to solve the problem of device malfunction due to bus failure during the use of the current parallel bus

Method used

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  • A parallel bus self-test method and system

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Embodiment Construction

[0017] The specific embodiments of the present invention will be further described below in conjunction with the drawings.

[0018] An embodiment of the parallel bus self-checking method of the present invention

[0019] The parallel bus to be tested in the present invention includes a bus interface, a master control element 101, a controlled element 103 of a bidirectional data interface, a controlled element 104 of a read-only one-way data interface, and a receiving device of a write-only one-way data interface. Control elements 105, of which 103, 104, 105 can be multiple. The main control element 101, the controlled element 103 of the two-way data interface, the controlled element 104 of the read-only one-way data interface, and the controlled element 105 of the write-only one-way data interface are all connected to the bus interface 301. The work of the control element is controlled by the main control element, and the controlled element follows the principle of time-sharing oc...

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Abstract

The present invention relates to a parallel bus self-inspection method and system. In the present invention, a data latch element is connected to the parallel bus to be tested, and other controlled elements connected to the parallel bus to be tested are released, so that the parallel bus to be tested All interface chips are in a high-impedance state; write fixed data to the data latch element through the main control element of the parallel bus to be detected, and read the data on the parallel bus through the main control element; then judge whether the data read by the main control element is It is consistent with the data written by the main control element, if consistent, it means that the parallel bus is normal, otherwise it means that the parallel bus is faulty. The invention realizes the reading and writing operation of the parallel bus to be tested by using the data latch technology when the bus is idle, and judges whether the bus is faulty according to the reading and writing results, so as to realize the self-inspection of the bus. The invention is simple and easy to implement, can realize the self-inspection of the parallel bus through few circuits, and avoids system data errors caused by parallel bus faults.

Description

Technical field [0001] The invention relates to a parallel bus self-checking method and system, belonging to the technical field of embedded automatic control. Background technique [0002] Parallel buses are widely used in embedded control systems. At present, bus expansion technology, timing control technology and even hot plug technology are mentioned in the application; these have promoted the application of parallel buses; relay protection measurement and control devices are also used more Parallel bus technology is used to realize the input and output of status data, as well as man-machine keyboard operation and liquid crystal display. Parallel bus applications include a main control element and multiple controlled elements. The interface chip of the controlled element uses the main control element to control the time-sharing to occupy the parallel bus or enter the high-impedance state, but on the physical connection, their interface chips are all hung up. On a bus. With ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/267
Inventor 周俊华王振华曹昆贺渊明胡凯利王晋华
Owner XUJI GRP
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