A Static Random Access Memory Unit Anti-Single Event Effect
An anti-single event effect, memory unit technology, applied in the direction of static memory, digital memory information, information storage, etc., can solve the problems of large device area and complex manufacturing process, achieve small parasitic capacitance, prolong feedback time, and improve anti-single Effect of Particle Flip Ability
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0040] like image 3 As shown, the present invention provides a single-event effect-resistant SRAM cell, the memory cell at least includes: a first cross-coupled inverter 10, a second cross-coupled inverter 20 and a transmission tube.
[0041] The first cross-coupled inverter 10 is composed of a first pull-up tube and a second pull-up tube. As an example, the first pull-up transistor and the second pull-up transistor are both PMOS transistors, which are respectively denoted as PU1 and PU2. The dimensions of the two pull-up tubes are closely matched to increase the stability of the memory cell.
[0042] The second cross-coupled inverter 20 is composed of a first pull-down tube and a second pull-down tube. As an example, the first pull-down transistor and the second pull-down transistor are both NMOS transistors, denoted as PD1 and PD2, respectively. The dimensions of the two pull-down tubes are closely matched to increase the stability of the storage unit.
[0043] The transf...
Embodiment 2
[0053] like Figure 4 As shown, the present invention provides another single-event effect-resistant SRAM cell, the memory cell at least includes: a first cross-coupled inverter 10 , a second cross-coupled inverter 20 and a transmission tube.
[0054] The first cross-coupled inverter 10 is composed of a first pull-up tube and a second pull-up tube. As an example, the first pull-up transistor and the second pull-up transistor are both PMOS transistors, which are respectively denoted as PU1 and PU2. The dimensions of the two pull-up tubes are closely matched to increase the stability of the memory cell.
[0055] The second cross-coupled inverter 20 is composed of a first pull-down tube and a second pull-down tube. As an example, the first pull-down transistor and the second pull-down transistor are both NMOS transistors, denoted as PD1 and PD2, respectively. The dimensions of the two pull-down tubes are closely matched to increase the stability of the storage unit.
[0056] ...
PUM
Abstract
Description
Claims
Application Information
- R&D Engineer
- R&D Manager
- IP Professional
- Industry Leading Data Capabilities
- Powerful AI technology
- Patent DNA Extraction
Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.
© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com