Method for generating verification platform file of integrated circuit and compiling system

Abstract

The present invention discloses a method for generating a verification platform file of an integrated circuit and a compiling system. The method comprises: obtaining design information of the integrated circuit according to a bus configuration; displaying the design information in a graphical user interface; modifying the design information according to a first user input; determine whether the design information is correct according to a register transfer level code of the integrated circuit; and when the design information is correct, generating the verification platform file of the integrated circuit according to the design information. According to the method for generating the verification platform file of the integrated circuit and the compiling system, a design verification environment of the integrated circuit can be quickly and automatically established, and the consistency of the verification platform file and the register transfer level code can be ensured, thereby reducing debugging time of design verification.

Description

technical field [0001] The present invention relates to integrated circuit design verification, and in particular to a method for generating integrated circuit testbench files and a related compiling system. Background technique [0002] Rapid advances in computing technology have made it possible to perform mega-operations per second on data sets as large as megabytes. These advances can be largely attributed to dramatic improvements in semiconductor design and manufacturing techniques, which have made it possible to integrate thousands of devices on a single chip. [0003] Integration density is also increasing rapidly to keep up with the insatiable demand for smaller, faster and more complex electronic devices and computers. As process technology advances, circuit designers and design verifiers face more difficult challenges. With the gradual increase in the complexity and device density of integrated circuit design, the design verification of integrated circuits requir...

AI Technical Summary

Problems solved by technology

As process technology advances, circuit designers and design verifiers face more difficult challenges

With the gradual increase in the complexity and component density of integrated circuit design, the design verification of integrated circuits (design verification) needs to spend more time and manpower to complete

As a result, circuit designers and design verifiers are finding it increasingly difficult to meet IC schedule deadlines

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