Elimination method of clock jitter in radio frequency direct band pass sampling digital receiving system

Abstract

The invention relates to an elimination method of clock jitter in a radio frequency direct band pass sampling digital receiving system. The method realizes elimination of the clock jitter in the radio frequency direct band pass sampling digital receiving system through adopting the non-uniform sampling output value of the radio frequency direct band pass sampling digital receiving system, the band pass sampling theory, the digital down-conversion theory and the feature of the radio frequency direct band pass sampling digital receiving system. The method can select different cascading series according to an actual radio frequency direct band pass sampling digital receiving demand so as to satisfy the demanded clock jitter elimination performance. The method of the invention is low in actual realization complexity and good in elimination effect, is easy for a hardware to realize, imposes no restriction on the type of the input signal of the radio frequency direct band pass sampling digital receiving system and is especially suitable for application of the radio frequency direct band pass sampling digital receiving system in modern communication, radar and high precision digital instrument.

Description

technical field [0001] The invention relates to a clock jitter elimination algorithm in a radio frequency direct band-pass sampling digital receiving system, and belongs to the fields of high-speed and high-precision analog-to-digital conversion technology and communication technology. Background technique [0002] High-speed and high-precision analog-to-digital converters are important components of modern electronic systems such as radars, medical instruments, and communication systems, and clock jitter is an important factor affecting the signal-to-noise ratio in analog-to-digital conversion. Traditional superheterodyne receivers and intermediate frequency receivers have the disadvantages of bulkiness and poor scalability due to the limitations of their architecture, and have gradually failed to meet the development needs of digital receiving systems. A new solution is to use RF direct bandpass sampling architecture. This receiving scheme uses the idea of ​​software radi...

AI Technical Summary

Problems solved by technology

Most of the existing clock jitter technologies are based on the fact that the input signal is an OFDM or LTE signal, and the signal is transformed into the frequency domain to eliminate the effect of clock jitter. This type of algorithm is currently a research hotspot at home and abroad, and there are also literatures showing that the estimated value of the jitter at the receiving end is fed back to the input At the transmitting end, digital pre-distortion technology is used to eliminate the influence of jitter, but it is required that the transmitting end and receiving end of the system can be well synchronized

In summary, the existing clock jitter elimination algorithm has the following limitations: (1) can only compensate narrowband signals (Rutten, R., L.J.Breems, and R.H.M. van Veldhoven.Digitaljitter-cancellationfornarrowbandsignals.inCircuitsandSystems, 2008.ISCAS2008.IEEEInternationalSymposiumon .2008.); (2) High computational complexity (Weller, D.S. and V.K.Goyal, Bayesian Post-Processing Methods for Jitter Mitigation in Sampling. Signal Processing, IEEE Transactionson, 2011.59(5): p.2112-2123.); (3) only suitable for specific Digital receiving systems for input signals, such as OFDM (Rabbi, M.F. and C.C. Ko. Modeling, estimation and mitigation of colored timing jitter for OFDMA system. in Consumer Communications and Networking Conference (CCNC)); therefore, research on a new method with wide application range and low computational complexity for analog input signals The clock jitter elimination algorithm of radio frequency direct band-pass sampling digital receiving system with few restrictions has important practical significance

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