Method for manufacturing through-hole silicon via

Abstract

The present invention relates to a method for manufacturing a through-hole silicon via (TSV), and the method for manufacturing a through-hole silicon via (TSV) employs the conventional trench insulation process to readily manufacture a through-hole silicon via (TSV) with achievement of an effective electrical insulation between the through-hole silicon via (TSV) and the silicon.

Description

technical field [0001] The present invention relates to a method for manufacturing through-silicon vias (TSVs), and more particularly, relates to a method for simply manufacturing through-silicon vias by using the existing trench-type component isolation process, and completing through-silicon vias. Method for fabricating through-silicon vias for effective electrical isolation between holes and silicon substrates. Background technique [0002] The three-dimensional stack package in the packaging technology of semiconductor integrated circuits is a package in which a plurality of chips with the same storage capacity are stacked, and is generally called a stack chip package (StackChipPackage). [0003] Stacked chip packaging technology has the advantages of being able to stack chips with a simple process to improve packaging performance, reduce production costs, and facilitate mass production. On the contrary, it also has the advantages of increasing the number and size of sta...

AI Technical Summary

Problems solved by technology

[0013] At this time, if the thickness of the oxidized part is uneven or thin, cracks (leak) may appear

Also, when the through-silicon via is penetrated to have a structure including a conductive substance, an oxide film, and silicon and operates as a metal-oxide-semiconductor (MOS), problems such as an increase in power loss (insertion loss) may occur due to an increase in capacitance. Negative impact

[0014] In particular, it becomes more difficult to isolate the sides of TSVs when the aspect ratio (aspectratio) is large

Images