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Integrated circuit layout optimizing method based on side-denoted short-circuit critical area network

A key area and optimization method technology, applied in the field of microelectronics, can solve the problems of inaccurate optimization results, failure to consider the impact, and inability to accelerate optimization, etc., to achieve the effects of reducing space complexity, layout optimization, and defect rate

Inactive Publication Date: 2016-04-20
XIDIAN UNIV
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  • Abstract
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  • Claims
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AI Technical Summary

Problems solved by technology

The disadvantage of this invention is that the circuit layouts that can be processed are limited and cannot accelerate the optimization of circuit layouts that do not have the same area
The influence of redundancy defects on the circuit layout is not considered, and the results of optimization are not accurate enough

Method used

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  • Integrated circuit layout optimizing method based on side-denoted short-circuit critical area network
  • Integrated circuit layout optimizing method based on side-denoted short-circuit critical area network
  • Integrated circuit layout optimizing method based on side-denoted short-circuit critical area network

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Embodiment Construction

[0043] The specific implementation steps of the present invention will be further described in detail below in conjunction with the figures.

[0044] According to attached figure 1 , realize the steps of the inventive method as follows:

[0045] Step 1. Input the original layout and mark the net

[0046] Input a layout image as the source image, use the matlab library function to convert the source image into a binary image, and then assign numbers to each connected area in the binary image in increasing order, that is, to number each line network. Such as figure 2 as shown, figure 2is the converted binary plane layout, which has 8 connected regions, that is, 8 nets, which are numbered 1...8 in columns;

[0047] Step 2. Calculate the weighted short-circuit critical area between nets

[0048] Such as image 3 shown, for n i row m i Arbitrarily shaped line network N of columns i and n j row m j Arbitrary shape line network N of columns j , where i,j=1,2,...8, i ima...

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Abstract

The invention provides an integrated circuit layout optimizing method based on a side-denoted short-circuit critical area network. The method is used for improving and designing layout wiring and increasing the finished product rate of integrated circuits. The method comprises the implementation steps that 1, an original layout is input, and nets are marked; 2, the weighted short-circuit critical area of the nets is calculated; 3, the side-denoted short-circuit critical area network based on an adjacency list is formed; 4, source points and sink points are added; 5, topological sorting is performed; 6, the critical area is obtained by solving critical paths; 7, the critical net to be optimized is obtained; 8 the critical net is optimized. According to method, the nets in the layout and the short-circuit critical area caused by redundancy material defects are associated, the space needed by storage is reduced, the time needed by optimization is shortened, the finished product rate of the layout can be effectively increased, and the reliability of the layout can be effectively improved; the method is a currently rare design method for optimizing the integrated circuit layout.

Description

technical field [0001] The present invention relates to the field of microelectronics and computer technology, and further relates to an integrated circuit layout optimization method based on an edge representation short circuit key area network in the field of image processing technology and integrated circuit technology. The invention constructs a short-circuit critical area network based on optimizing redundant object defects to improve the yield and reliability of the integrated circuit layout, and can be applied to optimize the design of the integrated circuit layout. Background technique [0002] With the increase of the complexity of integrated circuits, the reduction of chip area, feature size and gate oxide thickness, and the wide application of sub-wavelength lithography technology, the yield of integrated circuits (ICs) has been further reduced. In addition, problems such as yield loss caused by manufacturing defects and flatness caused by chemical mechanical poli...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F30/327
Inventor 王俊平伍尧曹洪花宁盼冯玉颖李超马塾亮
Owner XIDIAN UNIV
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