A method of forming a harp interlayer dielectric layer

Abstract

The invention provides a method of forming a HARP inter-layer dielectric layer. The method comprises the steps of providing a semiconductor substrate in which a gap to be filled is disposed; depositing a first HARP interlayer dielectric layer in the gap through the HARP process by using a silicon-containing precursor and an oxygen-containing precursor; processing the first HARP interlayer dielectric layer by using plasmas of the oxygen-containing precursor; repeating the steps S2 and S3 until the gap is filled. The invention enables the finally formed HARP interlayer dielectric layer to be more compact and higher in hardness through repeated deposition of the HARP interlayer dielectric layer and processing using the plasmas of the oxygen-containing precursor after the deposition each time, so that the HARP interlayer dielectric layer would not be sunken in subsequent CMP planarization.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a method for forming a HARP interlayer dielectric layer. Background technique [0002] One of the long-term challenges facing the development of semiconductor technology is the desire to continuously increase the density of circuit elements and the interconnections on the substrate without causing parasitic interactions with each other. Inappropriate interactions are generally prevented by providing gaps filled with interlevel dielectric layers to physically and electrically isolate devices. However, with the increasing demand for high integration and high performance of ultra-large-scale integrated circuits, semiconductor technology is developing towards technology nodes with feature sizes of 65nm or even smaller, so that the gap width is correspondingly reduced, and the aspect ratio is also increased. It is required to further improve the interstitial ability of thin fi...

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Problems solved by technology

[0007] Although the HARP process has the above-mentioned advantages, the HARP interlayer dielectric layer formed by the HARP process is usually loose and soft, and is prone to pit defects when planarized by a chemical mechanical polishing (CMP) process, such as figure 1 As shown, this kind of depression will provide an uneven interface (interface) for the metal interconnection in the back-end process. At the same time, it will seriously affect the formation of the subsequent contact hole process and affect the subsequent contact inter-connection.

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