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High-voltage VDMOS device and making method thereof

A manufacturing method and device technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problem that the size of DMOS cells cannot be further reduced

Inactive Publication Date: 2016-05-11
PEKING UNIV FOUNDER GRP CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The purpose of the present invention is to provide a high-voltage VDMOS device and its manufacturing method to solve the problem that the existing high-voltage VDMOS manufacturing process cannot further reduce the size of DMOS cells

Method used

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  • High-voltage VDMOS device and making method thereof
  • High-voltage VDMOS device and making method thereof
  • High-voltage VDMOS device and making method thereof

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Embodiment approach

[0049] Based on any of the above method embodiments, there are multiple ways to implement the above step 200 . A preferred embodiment is exemplified below: use photolithography and etching processes to form a trench on the front side of the wafer of the above-mentioned high-voltage VDMOS device; grow a sacrificial oxide layer on the surface of the trench to improve the shape of the trench through the sacrificial oxide layer. adjustment; removal of the sacrificial oxide layer.

[0050] By forming a sacrificial oxide layer on the surface of the trench and adjusting the shape of the trench, the radius of curvature of the fillet at the bottom of the trench can be increased.

[0051] Wherein, the thickness of the sacrificial oxide layer is greater than 1000 Angstroms. Preferably, the thickness of the sacrificial oxide layer is between 1000 angstroms and 10000 angstroms. Among them, 1 Angstrom is equal to 10 -10 Meter.

[0052] Preferably, the opening diameter of the initially f...

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Abstract

The invention discloses a high-voltage VDMOS device and a making method thereof. A grid making method of the high-voltage VDMOS device comprises the following steps of making a groove on a front side of a wafer of the high-voltage VDMOS device; making a grid oxide layer on a front side of the wafer where the groove is formed; and making a grid on a front side of the wafer where the grid oxide layer is formed, wherein a mask layer window used for making the grid aligns the groove, and a width of the mask layer window used for making the grid is greater than an opening width of the groove. Through the above technology process, the grid is filled into the groove. Under the condition that an effective length of the grid is not changed, a transverse width of the grid is reduced so that a cellular integration degree is increased under the condition of a same chip area or a chip area is reduced under the condition of a same current processing capability. Besides, because the effective length of the grid is not reduced, a large influence on performance of other electrical parameters is not generated.

Description

technical field [0001] The invention relates to the technical field of manufacturing semiconductor devices, in particular to a high-voltage VDMOS (vertical double-diffused metal oxide semiconductor) device and a manufacturing method thereof. Background technique [0002] High-voltage VDMOS generally adopts a planar cell structure to obtain high breakdown voltage, such as figure 1 shown. As the competition in the VDMOS product market becomes more and more fierce, many manufacturers have launched corresponding miniature products one after another. The reduction in product size is mainly achieved by reducing the size of the cell. An important parameter of high-voltage VDMOS is the on-resistance (RDSON), and an important component of the on-resistance is the resistance of the surface charge accumulation layer formed on the layer directly below the gate. As the gate length decreases, the on-resistance of the high-voltage VDMOS will increase. In order to avoid excessive on-res...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L21/28H01L29/78H01L29/423
Inventor 蔡远飞何昌姜春亮
Owner PEKING UNIV FOUNDER GRP CO LTD