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Field effect transistor and method

A field effect transistor, single crystal technology, used in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc.

Active Publication Date: 2016-05-11
HRL LAB
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0012] Unfortunately, the process of forming MOCVDAlN may degrade the PECVDSiN film already deposited on the semiconductor

Method used

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  • Field effect transistor and method
  • Field effect transistor and method
  • Field effect transistor and method

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Experimental program
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Effect test

Embodiment Construction

[0024] In the following description, numerous specific details are given to clearly describe various specific embodiments disclosed herein. However, it will be understood by those skilled in the art that the invention claimed herein may be practiced without all of the specific details discussed below. In other instances, well-known features have not been described in order not to obscure the invention.

[0025] figure 1 A diagram of a III-nitride field effect transistor (FET) according to the present disclosure is shown. The FET has a buffer layer 14 formed on a substrate 12 . A channel layer 16 is formed on the buffer layer 14 and a barrier layer 18 is formed on the channel layer 16 .

[0026] Substrate 12 material can be silicon (Si), silicon carbide (SiC), sapphire (Al 2 o 3 ), gallium nitride (GaN) or aluminum nitride (AlN).

[0027] Buffer layer 14 may be a stack of Ill-nitride materials grown on substrate 12 by chemical vapor deposition or molecular beam epitaxy. ...

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Abstract

A field-effect transistor (FET) includes a plurality of semiconductor layers, a source electrode and a drain electrode contacting one of the semiconductor layers, a first dielectric layer on a portion of a top semiconductor surface between the source and drain electrodes, a first trench extending through the first dielectric layer and having a bottom located on a top surface or within one of the semiconductor layers, a second dielectric layer lining the first trench and covering a portion of the first dielectric layer, a third dielectric layer over the semiconductor layers, the first dielectric layer, and the second dielectric layer, a second trench extending through the third dielectric layer and having a bottom located in the first trench on the second dielectric layer and extending over a portion of the second dielectric, and a gate electrode filling the second trench.

Description

[0001] Cross References to Related Applications [0002] This application is related to US Patent Application Serial No. 13 / 456,039, filed April 25, 2012. This application also claims priority and benefit to U.S. Patent Application Serial No. 14 / 041,667, filed September 30, 2013, and U.S. Patent Application Serial No. 14 / 290,029, filed May 29, 2014, which are adopted in their entirety Incorporated herein by reference. [0003] Statement Regarding Federal Funding [0004] This invention was made with support under US Government Contract DE-AR-0000117. The US Government has certain rights in this invention. technical field [0005] The present disclosure relates to III-nitride field effect transistors (FETs) and in particular to insulated gates for FETs. Unless otherwise stated, this article pertains to Ill-nitride insulated gate transistors with passivation. Background technique [0006] Ill-nitride transistors are promising for high speed and high power applications suc...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L21/336
CPCH01L29/2003H01L29/41766H01L29/4236H01L29/42376H01L29/513H01L29/66462H01L29/7786H01L29/66666H01L29/7783H01L29/7827
Inventor 楚荣明玛丽·Y·陈李子健“雷伊”卡里姆·S·布特罗陈旭大卫·F·布朗亚当·J·威廉姆斯
Owner HRL LAB