Novel 10 gigabit Ethernet parallel CRC encoding and decoding method

Abstract

The present invention provides a novel 10 gigabit Ethernet parallel CRC encoding and decoding method. Compared with a traditional 10 gigabit Ethernet parallel CRC encoder and decoder which cannot combine calculation speed and occupancy of resources, the novel 10 gigabit Ethernet parallel CRC encoding and decoding method is able to simply solve the problem of the CRC encoding caused by variable-length bytes through encoding preprocessing at encoding so as to simplify the design of a CRC encoding circuit, and separate the FCS region of an Ethernet frame through decoding preprocessing and recover the data output by an encoding preprocessing module at decoding so as to simplify the design of the CRC verification circuit. The CRC encoder and decoder are compatible to the current method through switching work modes, speed up the calculation through the designed work modes, and are small in calculation circuit time relay and small in consume resources so as to be compatible to the calculation speed and the occupancy of resources.

Description

technical field [0001] The invention relates to the technical field of fast coding and decoding of Ethernet communication, in particular to a novel 10 Gigabit Ethernet parallel CRC coding and decoding method. Background technique [0002] Ethernet is the most common communication protocol standard adopted by existing local area networks today, and a cyclic redundancy check code (Cyclic Redundancy Check, CRC) needs to be used in Ethernet communication to implement error control on data. The internal data width adopted by 10 Gigabit Ethernet is as high as 64 bits, which is much larger than the internal data width of 8 bits or 4 bits of Gigabit and below bandwidth Ethernet. [0003] The traditional 10 Gigabit Ethernet parallel CRC codec mainly has the following three methods: 1. Cross-pipeline method. This method uses 8-bit CRC-32 circuits and 64-bit CRC-32 circuits to perform pipeline calculations on data. The 64-bit aligned data uses a 64-bit parallel input CRC-32 circuit, a...

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Problems solved by technology

However, none of the above three methods can take into account the calculation speed and resource occupation at the same time. The output delay of the cross-flow water generator may be 7 clock cycles at most. The delay of the operation circuit of the cascade structure method is very large, and the repeated CRC logic method occupies logic resources. many

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