Memory control circuit and memory

Abstract

The invention relates to a memory control circuit and a memory. The memory control circuit comprises a source line gate tube and a word line gate tube, the word line gate tube is connected with a memory cell, the source line gate tube is connected with the memory cell through a local source line, the memory control circuit also comprises a compensation unit, and the compensation unit discharges electricity to the local source line in the reading operation in order to reduce the voltage of the local source line. The arrangement of compensation unit reduces the voltage of the local source line in the reading operation and increases a voltage difference between the local word line and the local source line, and the reading time needed from address input to address output becomes short with the increase of the current of the memory cell, so the reading speed of the memory is improved.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a memory control circuit and memory. Background technique [0002] With the continuous improvement of semiconductor manufacturing technology and integrated circuit design capabilities, people have been able to integrate processors, memory, analog circuits, interface logic and even radio frequency circuits into one chip, which is the System-on-Chip (System-on-Chip, SoC). With the continuous increase of data throughput and the requirement of low power consumption of the system, the memory requirement of system-on-chip is increasing. It is predicted that about 90% of the silicon chip area will be occupied by memories with different functions in the future, and embedded memories will become the decisive factor dominating the entire system. Represented by flash memory (flash) and Electrically Erasable Programmable Read-Only Memory (EEPROM), non-volatile memory has be...

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Problems solved by technology

[0004] However, in the prior art, due to the small size of the word line gating transistor M1 and the source line gating transistor M2, their current conduction capability is weak; during the read operation of the memory, if a single memory cell has a large current, due to the source line selection The conduction ability of the pass tube M2 is weak, the local source line voltage rises, the voltage difference between the drain and source of the memory cell decreases, and the conduction current of the memory cell becomes smaller, resulting in a decrease in the read speed, and the address input to the data output. The required read time (Taa) becomes longer, reducing the efficiency of the memory

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