Manufacturing method of semiconductor device
A semiconductor and strain relief technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., to achieve the effect of improving electronic insulation
Active Publication Date: 2018-10-26
TAIWAN SEMICON MFG CO LTD
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Problems solved by technology
Therefore, although the existing semiconductor manufacturing process has been widely used, it still does not meet the needs of various aspects
Method used
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[0042] The following disclosure provides many different embodiments or examples for implementing different features of the invention. The composition and layout of specific examples are described below to simplify the present invention. Of course these are examples only and are not intended to be limiting. For example, where it is stated that a first feature is formed on or over a second feature, then may include embodiments where the first and second features are formed in direct contact; and may also include embodiments, Where additional features can be formed between the first and second features so that the first and second features are not in direct contact. In addition, the present invention may repeat element numbers and / or characters in each example. The purpose of repetition is for simplicity and clarity, but not to determine relative relationships between the various embodiments and / or configurations discussed.
[0043] In addition, relative terms in space, such a...
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The present invention relates to a method of manufacturing a semiconductor device. The present disclosure provides a method of forming a fin transistor (FinFET) device. The method includes forming a first strain relief buffer (SRB) stack over a substrate. There is a lattice mismatch between the first SRB stack and the substrate, which produces a helical dislocation defect characteristic in the first SRB stack. The method also includes forming a patterned dielectric layer on the first SRB stack. The patterned dielectric layer includes trenches extending therethrough. The method also includes forming a second SRB stack above the first SRB stack within the trench. There is a lattice mismatch between the second SRB stack and the substrate, so that the upper part of the second SRB stack has no helical dislocation defects. In addition, a buffer layer is arranged in the first and second SRB stacks to enhance electronic insulation; an SLS layer is arranged in the second SRB stack to enhance the effect of trapping spiral dislocation defects on the upper part of the substrate.
Description
technical field [0001] The present disclosure relates to the field of semiconductor integrated circuits, in particular to a semiconductor integrated circuit with fin features and a manufacturing method thereof. Background technique [0002] In pursuit of higher device density, higher performance and lower cost, the semiconductor industry has advanced to nano-node process technology. In the evolution of integrated circuits (ICs), functional density (i.e., the number of interconnected devices per unit silicon area) has generally increased, while geometric size (i.e., the smallest component or line that can be produced by the process used) has decreased. Small. Size reduction processes generally provide benefits by increasing production efficiency and reducing associated costs; however, they also increase the complexity of processing and manufacturing integrated circuits. In order to realize these advantages, it is necessary to develop the related integrated circuit manufactu...
Claims
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IPC IPC(8): H01L21/8252H01L21/02
CPCH01L21/02381H01L21/02455H01L21/02538H01L21/8252H01L21/02507H01L21/02639H01L21/76224H01L29/1054H01L29/32H01L29/66795H01L21/3247
Inventor 马克范达尔乔治凡利亚尼提斯麦特西亚斯帕斯拉克马汀克里斯多福荷兰
Owner TAIWAN SEMICON MFG CO LTD