Electronic package structure and the manufacturing method thereof

Abstract

An electronic package structure and a manufacturing method thereof. The method includes forming a circuit layer on a conductor; disposing an electronic element on the circuit layer; forming an insulating layer over the conductor to encapsulate the electronic element and the circuit layer; and removing parts of the conductor to form a plurality of conductive bumps, thereby facilitating alignment of conductive bumps with the contact points when the electronic element is mounted on the circuit board by the surface mount technology (SMT) so as to effectively reduce the defect rate of SMT processing.

Description

technical field [0001] The invention relates to a packaging technology, in particular to a method for manufacturing an electronic packaging structure. Background technique [0002] With the vigorous development of the electronic industry, electronic products are gradually moving towards the trend of multi-function and high performance. In order to meet the packaging requirements of miniaturization of semiconductor packages, there is a tendency to reduce the thickness of the package substrate carrying the chip. [0003] Figure 1A to Figure 1D It is a schematic cross-sectional view of a conventional manufacturing method of a coreless semiconductor package 1 . [0004] like Figure 1A As shown, a circuit layer 11 is formed on a carrier board 10, wherein the circuit layer 11 includes a die placement pad 111 and a plurality of electrical connection pads 112, and these electrical connection pads 112 surround the die placement pad 111 . [0005] like Figure 1B As shown, a se...

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Problems solved by technology

[0008] However, in the existing manufacturing method of the semiconductor package 1, the exposed surface of the circuit layer 11 is flush with the bottom of the insulating layer 13, so when the semiconductor package 1 is designed with Surface Mounting Technology (SMT) When placed on a circuit board, the conductive elements 16 on these circuit layers 11 are not easy to align with the contacts on the circuit board, resulting in an increase in the defect rate of the SMT process

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