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A low-power combined encoding and decoding circuit and encoding and decoding method applied to a network on chip

A network-on-chip, low-power technology, applied in the field of encoding and decoding circuits, can solve the problems of insignificant overall effect, large interconnection network power consumption, high flip rate, etc., to overcome its own area overhead, reduce transmission power consumption, The effect of low dynamic power consumption

Active Publication Date: 2019-03-08
黄山市开发投资集团有限公司
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  • Claims
  • Application Information

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Problems solved by technology

[0002] As the feature size of integrated circuits shrinks, the clock frequency increases, the number of transistors integrated on a single chip exceeds 1 billion orders of magnitude, and the density of interconnection lines continues to increase, energy consumption has gradually become the main bottleneck of chip design; it can be seen that the network on chip ( Network On Chip (NoC) power consumption has become a key factor affecting chip performance; the dynamic power consumption of NoC mainly includes node power consumption and network power consumption, node power consumption is the power consumption generated by the internal operation of routing nodes, and network power consumption is the power consumption of data The power consumption generated on the interconnection network when transmitting from the source node to the destination node in the network; when a large amount of data is transmitted from the source node to the destination node in the NoC, the high turnover rate between adjacent transmission data causes the NoC to generate Large interconnect network power consumption
[0003] In the prior art, bus inversion (Bus Invert, BI) coding is a low-power coding method commonly used in data buses, and Gray code coding is a low-power coding method commonly used in address buses. Power consumption coding instead of NoC in low power consumption design; BI code is suitable for random data, which needs to add extra redundant flag bits, and the effect decreases with the increase of data bit width, which has great limitations for continuous data The Gray code is suitable for continuous data and has great limitations for random data; for the existing NoC platform, the transmitted data includes both random data and continuous data, using BI code alone or Gray code alone, NoC The power consumption can only be reduced by a small part, and coupled with the area overhead of the encoding circuit itself, the overall effect of reducing power consumption is very insignificant. At present, no low-power design in which BI codes and Gray codes are jointly applied to NoCs has been found.

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Embodiment Construction

[0044] In this embodiment, the on-chip network is the smallest two-dimensional network of M×N=2×2; and it is used to transmit external data packets; the routing node that receives the data packet is defined as the source node, and the routing node that outputs the data packet is the destination node ;The data packet is composed of n=5 microchips, which are respectively 1 header microchip, n-2=3 individual microchips and 1 tail microchip; each microchip includes a microchip header, a binary microchip counter, a binary packet Counter, low-order data; M and N are integers greater than or equal to 2; n is an integer greater than or equal to 3;

[0045] Such as figure 1 As shown, node 1 is the source node, node 4 is the destination node, a low-power combined encoding and decoding circuit applied to the network on chip, an encoding circuit is set at the input end of the source node, and an encoding circuit is set at the output end of the destination node With decoding circuit;

[...

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Abstract

The invention discloses an encoding and decoding circuit based on low power consumption combination applied to a network on chip and an encoding and decoding method thereof. The encoding and decoding circuit is characterized in that an encoding circuit is arranged at the input end of a source node, and a decoding circuit is arranged at the output end of a destination node; the encoding circuit comprises an encoding judgment splitting module, four Hamming distance calculating modules, four data turning modules, a gray code encoding module, and a data encoding packaging module; and the decoding circuit comprises a decoding judgment splitting module, four data anti-turning modules, a gray code decoding module, and a data decoding packaging module. The turning rate of transmitted data can be reduced, so that the power consumption of the whole network on chip is reduced, and correct data transmission is ensured.

Description

technical field [0001] The invention belongs to the technical field of communication of integrated circuit on-chip networks, and in particular relates to an encoding and decoding circuit and an encoding and decoding method for combination of packet inversion encoding and Gray code encoding with low power consumption applied to an on-chip network. Background technique [0002] As the feature size of integrated circuits shrinks, the clock frequency increases, the number of transistors integrated on a single chip exceeds 1 billion orders of magnitude, and the density of interconnection lines continues to increase, energy consumption has gradually become the main bottleneck of chip design; it can be seen that the network on chip ( Network On Chip (NoC) power consumption has become a key factor affecting chip performance; the dynamic power consumption of NoC mainly includes node power consumption and network power consumption, node power consumption is the power consumption genera...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M7/16H03M7/26
CPCH03M7/16H03M7/26
Inventor 杜高明马世碧张多利宋宇鲲李向阳尹勇生
Owner 黄山市开发投资集团有限公司
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