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Semiconductor device, manufacturing method thereof, and electronic equipment including the same

A semiconductor and device technology, applied in the field of electronic equipment, can solve the problem of difficulty in preventing the PTS layer dopant from entering the channel region, etc.

Active Publication Date: 2019-12-03
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, it is difficult to prevent dopants in the PTS layer from entering the channel region using conventional ion implantation or thermal diffusion methods

Method used

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  • Semiconductor device, manufacturing method thereof, and electronic equipment including the same
  • Semiconductor device, manufacturing method thereof, and electronic equipment including the same
  • Semiconductor device, manufacturing method thereof, and electronic equipment including the same

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Embodiment Construction

[0015] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

[0016] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions / layers with different shapes, ...

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PUM

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Abstract

The invention discloses a semiconductor and a manufacturing method thereof and electronic equipment comprising the semiconductor. According to the embodiment, the semiconductor can comprise a substrate, a fin, a source region layer, a drain region layer, a gate stack and a punch-through stop (PTS) layer, wherein the fin is formed on the substrate and extends along a first direction; the fin comprises a first side surface and a second side surface which are located at two opposite ends in the first direction; the source region layer and the drain region layer are formed on the first side surface and the second side surface of the fin respectively; the gate stack is formed on the substrate and extends along a second direction intersected with the first direction; the gate stack is intersected with the fin to limit a channel region in the fin; the punch-through stop (PTS) layer is formed at the bottom part of the channel region in the substrate; and the PTS layer has doping concentration distribution with high concentration in two sides and low concentration in the middle along the first direction at the lower part of the fin.

Description

technical field [0001] The present disclosure relates to the field of semiconductors, and in particular, to a semiconductor device having a punchthrough stopper (PTS) layer capable of inhibiting dopants in the PTS from entering a channel region, a manufacturing method thereof, and an electronic device including the semiconductor device. Background technique [0002] As the size of planar semiconductor devices becomes smaller and smaller, the short channel effect becomes more and more obvious. For this reason, three-dimensional semiconductor devices such as Fin Field Effect Transistors (FinFETs) have been proposed. In general, a FinFET includes a fin formed vertically on a substrate and a gate intersecting the fin. [0003] In particular, in a bulk FinFET (i.e., a FinFET formed on a bulk semiconductor substrate, and more specifically, a fin formed from and thus in contact with the bulk semiconductor substrate), there may be Leakage through the portion of the substrate below...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L29/78H01L29/10H01L21/265
CPCH01L21/265H01L29/1083H01L29/66795H01L29/785
Inventor 朱慧珑魏星
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI