MOS transistor and forming method thereof
A MOS transistor and semiconductor technology, which is applied in the manufacturing of semiconductor devices, electric solid-state devices, and semiconductor/solid-state devices.
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no. 1 example
[0036] Figure 5 to Figure 9 It is a schematic structural diagram of the formation process of the MOS transistor in the first embodiment of the present invention.
[0037] refer to Figure 5 , a semiconductor substrate 200 is provided, the semiconductor substrate 200 has a center region (II region) and an edge region (I region), and the surface of the semiconductor substrate 200 has a first interlayer dielectric layer 220 and a first interlayer dielectric layer penetrating the center region 220 thickness of opening 221.
[0038] The semiconductor substrate 200 provides a process platform for the subsequent formation of MOS transistors.
[0039] The semiconductor substrate 200 can be monocrystalline silicon, polycrystalline silicon or amorphous silicon; the semiconductor substrate 200 can also be semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, etc.; the semiconductor substrate 200 can also be other semiconductor materials Semiconducto...
no. 2 example
[0065] Figures 10 to 11 It is a schematic diagram of the formation process of the MOS transistor in the second embodiment of the present invention.
[0066] The difference between the method in this embodiment and the method in the first embodiment is that an adhesive layer is formed on the surfaces of the metal layer 243 , the metal gate structure 245 and the first interlayer dielectric layer 220 . The same parts of this embodiment and the first embodiment will not be described in detail.
[0067] refer to Figure 10 , Figure 10 for in Figure 7 Based on the schematic diagram formed, an adhesive layer 251 is formed on the surfaces of the metal layer 243 , the metal gate structure 245 and the first interlayer dielectric layer 220 .
[0068] The function of the bonding layer 251 is to bond with the metal layer 243 and the second interlayer dielectric layer formed subsequently to prevent the second interlayer dielectric layer in the edge region from falling off the surface...
no. 3 example
[0076] Figures 12 to 14 It is a schematic diagram of the formation process of the MOS transistor in the third embodiment of the present invention.
[0077] The difference between the method in this embodiment and the method in the first embodiment is that the bonding layer covering the first interlayer dielectric layer 220 in the edge region is formed while the metal gate structure 245 is formed. The same parts of this embodiment and the first embodiment will not be described in detail.
[0078] refer to Figure 12 , Figure 12 for in Figure 5 Based on the schematic diagram formed, the top surface of the first interlayer dielectric layer 220 and the opening 221 (refer to Figure 5 ) A gate dielectric material layer 230 is formed on the bottom and sidewalls; a gate electrode material layer 231 is formed on the surface of the gate dielectric material layer 230, and the entire gate electrode material layer 231 surface in the central region is higher than the first interlaye...
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