Intra-cluster storage concurrent access local-preference switching circuit in array processors

Abstract

The invention discloses an intra-cluster storage concurrent access local-preference switching circuit in array processors, is mainly applicable to data concurrent access functions of intra-cluster distributed storage structures in the array processors, belongs to the technical field of integrated circuit design, and aims at reducing storage access delay, improving access bandwidth and improving a resource utilization rate through a multilevel switching structure and a local-preference access strategy. According to the design, a three-level switching structure of local switching+global switching+local switching is employed; the concurrent access of 4*4 array processors to 16 distributed storage blocks is realized, the concurrency of local data access is improved, the global access delay is reduced, and the storage structures are simplified.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design, and in particular relates to data parallel access of a distributed storage structure in a 4*4 processor array cluster in an array processor. Background technique [0002] With the development of integrated circuit technology, the traditional processor performance improvement method is still used: continuously increasing the main frequency and developing instruction set parallelism, there are problems of rapid increase in design complexity and excessive power consumption, and the continuous increase of main frequency makes The problem of "storage wall" is becoming more and more prominent. In order to adapt to the development of integrated circuit technology and maintain Moore's Law, integrating dozens or even hundreds of simple processor cores on a single chip has become a trend in the development of computer architecture. However, with the advancement of technology, more and mor...

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Problems solved by technology

In the traditional NoC (Network on Chip) interconnection, on the one hand, the data access delay is relatively large, and the general read / write delay is as high as dozens of clock cycles, which is equivalent to 1~2 cycles of operation-level or data-level operations. In contrast, the delay is too large, which makes it difficult to meet the real-time requirements of the application; on the other hand, the circuit size of a single processing unit of a light-core array processor is about 2000 logic units, and the resources occupied by a 4-channel virtual channel router are about Six times the processing unit, resulting in communication resources far greater than computing resources, low resource utilization

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