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Dielectric capacitor based on soi process

A dielectric capacitor and process technology, applied in capacitors, circuits, electrical components, etc., can solve problems such as circuit performance not meeting expected requirements

Active Publication Date: 2019-12-10
CSMC TECH FAB2 CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The parasitic capacitance will bring some unknown effects to the circuit design, so that the circuit performance cannot meet the expected requirements

Method used

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  • Dielectric capacitor based on soi process

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Embodiment Construction

[0016] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0017] figure 1 It is a schematic cross-sectional view of a dielectric capacitor based on the SOI process in an embodiment, and the parasitic capacitance between the plate and the substrate of the dielectric capacitor based on the SOI process is relatively small. see figure 1 , the dielectric capacitor based on the SOI process includes bottom silicon 102, buried oxide layer 104, top silicon 106, interlayer dielectric layer 108, lower plate 110, insulating layer 112, upper plate 114, shallow trench isolation structure 116, Deep trench isolation structure 118 and substrate lead-out region 120 .

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Abstract

The invention relates to a dielectric capacitor based on SOI technology, which sequentially includes from bottom to top: bottom silicon; a buried oxide layer formed on the surface of the bottom silicon; a top silicon formed on the surface of the buried oxide layer; an interlayer dielectric layer on the top silicon surface; a lower electrode plate, an insulating layer and an upper electrode plate formed on the interlayer dielectric layer in sequence; the lower electrode plate, the insulating layer and the upper electrode plate constitute the The main part of the dielectric capacitor; the dielectric capacitor also includes: a shallow trench isolation structure formed on the top layer of silicon for isolating the active area; formed under the lower plate and penetrating the top layer of silicon to connect with the top layer of silicon. Described is a deep trench isolation structure connected by buried oxide layers. The above-mentioned dielectric capacitor based on the SOI process can effectively reduce the parasitic capacitance effect of the dielectric capacitor.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a dielectric capacitor based on SOI technology. Background technique [0002] In semiconductor preparation, dielectric capacitors based on SOI (Silicon-On-Insulator, silicon on insulating substrate) technology are widely used in analog radio frequency circuits. There are parasitic capacitances in the upper plate, lower plate and substrate of the traditional dielectric capacitor based on SOI process. The parasitic capacitance will bring some unknown effects to the circuit design, so that the circuit performance cannot meet the expected requirements. Contents of the invention [0003] Based on this, it is necessary to provide a dielectric capacitor based on SOI technology that can reduce the effect of parasitic capacitance. [0004] A dielectric capacitor based on the SOI process, comprising from bottom to top in sequence: bottom silicon; a buried oxide layer formed on t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/12H01L27/13H01L23/64H10N97/00
CPCH01L27/1203H01L27/13H01L28/40H01L23/642H01L23/66
Inventor 刘新新何小东
Owner CSMC TECH FAB2 CO LTD