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FIR filter bank and filtering method

A filter bank and controller technology, applied in impedance networks, digital technology networks, electrical components, etc., can solve the problem of inability to provide filter bank reconfigurability, lack of single filter reconfigurability, and low resource utilization. And other issues

Active Publication Date: 2017-05-10
SANECHIPS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, currently in the design of application specific integrated circuits (ASIC, Application Specific Integrated Circuit), although there have been reconfigurable improvements for a single filter structure, the reconfigurability of filter banks cannot be provided; and, currently The emerging reconfigurable scheme of filter banks is implemented by modifying the connection relationship between filters, but lacks the reconfigurability of a single filter, and the resource utilization is low.
It is impossible to achieve reconfigurable, reusable, flexible and configurable in the case of long-term coexistence of multiple communication standards

Method used

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  • FIR filter bank and filtering method

Examples

Experimental program
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Embodiment 1

[0041] The basic idea of ​​the technical solution of the embodiment of the present invention is to consider all the hardware resources of the filter in a unified manner, so that the filtering resources can be reorganized according to different application scenarios, thereby forming different filter bank structures, and realizing the filter Group reconfigurability.

[0042] see figure 1 , which shows the structure of a FIR filter bank 10 proposed by the embodiment of the present invention. Such as figure 1As shown, the FIR filter bank 10 includes two components: a data processing circuit 101 and a control circuit 102, and these two components are coupled to each other. Understandably, since this embodiment is an example description of the structure of the FIR filter bank 10, therefore, for the external circuits and electrical components related to the FIR filter bank 10, this embodiment does not specifically describe them in detail, and those skilled in the art The relevant ...

Embodiment 2

[0061] see Figure 6 , which shows a filtering method applied to the FIR filter bank described in the foregoing embodiment, the specific structure of the FIR filter bank is as described in the foregoing embodiment, and will not be repeated here, and the filtering method may include:

[0062] S601: After the input port receives the input data, transmit the input data to the data flow bus array;

[0063] Specifically, transmitting the input data to the data stream bus array may include:

[0064] When the input data is transmitted to the data stream bus in the data stream bus array, the ID is correspondingly identified, and the corresponding identification bit dv used to represent the data as new data is set to valid.

[0065] S602: The cache resource blocks in the cache resource pool receive the data transmitted by the data stream bus array according to the control of the data flow controller, and control them through the data flow controller according to the filter order, numb...

Embodiment 3

[0076] Taking two series filters as an example, set the first-stage filter to have 12 coefficients with even symmetry, 2 times decimation, and 3 times the input multiplexing ratio; the second-stage filter has 47 coefficients with odd symmetry, 2 times decimation, 6 times the input multiplexing ratio. Based on the FIR filter bank and filtering method described in the foregoing embodiments, the specific implementation process is as follows:

[0077] Set the first-stage filter to occupy ID0 and ID1 two cache resource blocks, the cache cascade switch of cache resource block ID0 is set to be connected to the data flow bus array, and the input data of the register group of cache resource block ID0 is controlled by the data flow bus Provided by the array; the cache cascade switch of the cache resource block ID1 is set to be connected to the previous cache resource block ID0, and the input data of the register group of the cache resource block ID1 is provided by the cache resource blo...

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PUM

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Abstract

The embodiment of the invention discloses a FIR (Finite Impulse Response) filter bank and a filtering method. The FIR filter bank comprises a control circuit and a data processing circuit that are coupled with each other. The data processing circuit comprises a data flow bus array, a buffer memory resource pool, an arithmetic logic unit (ALU) resource pool, and an accumulator resource pool. The control circuit comprises a data flow controller, a buffer memory resource mapping device, a filtering coefficient memory, an ALU controller, an accumulating resource organizer, and an output sequential controller.

Description

technical field [0001] The invention relates to digital signal processing technology, in particular to a Finite Impulse Response (FIR, Finite Impulse Response) filter bank and a filtering method. Background technique [0002] In recent years, due to the software-defined concepts such as software-defined network (SDN, Software Defined Network), software-defined storage, and software-defined cloud computing, the demand for functional flexibility, easy scalability, and reconfigurability of hardware products is increasing. [0003] FIR filters are the most basic components in digital signal processing systems, and are widely used in communication, image processing, pattern recognition and other fields, for example, digital up converters (DUC, Digital Up Converter) and A link of a Digital Down Converter (DDC, Digital Down Converter) includes a large number of FIR filters. [0004] However, currently in the design of application specific integrated circuits (ASIC, Application Spe...

Claims

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Application Information

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IPC IPC(8): H03H17/02
CPCH03H17/02
Inventor 马传文杨丽宁温龙
Owner SANECHIPS TECH CO LTD
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