Method for re-sequencing scan chains

Abstract

The embodiment of the invention discloses a method for re-sequencing scan chains, which is applied to the technical field of integrated circuit scanning test. The chip area is reduced, the additional expenditure brought by the operation of inserting the scan chains into a buffer is reduced and the wiring jamming degree is reduced. In the embodiment of the invention, the method comprises the following steps: forming a set G by all registers in the scan chains which are not re-sequenced; randomly selecting one register from the set G and using the selected register as a present register; selecting the register having the minimal consumption value with the present register from the rest registers in the set G and using as a to-be-re-sequenced register; if the Manhattan distance between the to-be-re-sequenced register and the present register is not more than 1max, adding the present register into a new register sequence; using the to-be-re-sequenced register as the present register and executing the steps till no register element exists in the set G.

Description

technical field [0001] The invention relates to the technical field of integrated circuit scan testing, in particular to a scanning chain reordering method. Background technique [0002] The scan chain is an important part of the testability design of the chip. It replaces the ordinary registers used in the chip with the multi-input and output scan registers with scanning functions, and connects them end to end in series to achieve additional test functions. The lines introduced into the design by inserting scan chains take up some of the routing resources. In the test mode, the data path of the scan chain must also meet timing check constraints such as setup time and hold time, and the buffer introduced thereby further increases the area and power consumption of the integrated circuit. [0003] Reordering the scan chain is a way to reduce the area and power consumption of the integrated circuit. The scan chain reordering method is to reconnect the scan registers on the sca...

AI Technical Summary

Problems solved by technology

Although the existing resequencing method has achieved certain results in reducing circuit power consumption, it has brought another problem, that is, wiring congestion, and with the development of integrated circuit technology, the circuit integration level is getting higher and higher. When the process node of integrated circuit design is reduced to below 65NM, in order to meet the setup time and hold time constraints of the scan chain, more and more buffer units are required on the scan chain, resulting in more and more area and power consumption overhead , resulting in more and more severe layout and routing congestion, which adversely affects chip performance, power consumption, and area

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