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Planar gate groove-type super junction device and manufacturing method thereof

A manufacturing method and trench-type technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of leakage devices, failures, and a major hidden danger of device reliability, so as to prevent device failures and improve reliability. performance, improve product yield

Active Publication Date: 2017-05-17
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] The existence of hole defects 105 in the trench-type super junction is a major hidden danger to the reliability of the device, and may even cause leakage and other situations to cause the device to fail

Method used

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  • Planar gate groove-type super junction device and manufacturing method thereof
  • Planar gate groove-type super junction device and manufacturing method thereof
  • Planar gate groove-type super junction device and manufacturing method thereof

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Embodiment Construction

[0058] Before describing the embodiments of the present invention, let me introduce the problems of device failure and reliability reduction caused by hole defects in existing planar gate trench super junction devices:

[0059] Such as Figure 4 As mentioned above, it is the layout of the existing planar gate trench type super junction device; Figure 5 is along Figure 4 Sectional view of line BB in ; Figure 6 is along Figure 4 Sectional view of CC line in ; Figure 4 Among them, the straight line AA represents the boundary line of the field oxide layer 110, Figure 4 The left side of the straight line AA in FIG. 2 represents the active region, and the right side represents the outer region of the active region where the field oxide layer 110 is formed. The P-type thin layer 104 and the N-type thin layer 102 are formed on the entire active region and the semiconductor substrate 101 outside the active region. The overlapping structure of the P-type thin layer 104 and t...

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Abstract

The present invention discloses a planar gate groove-type super junction device. The device comprises: a groove-type super junction; a top field oxide layer of a groove-type super junction formed at the outer side of an active area; and polysilicon gates of each N-type film surface of the groove-type super junction formed in the active area. Each polysilicon gate extends to the surface of the corresponding field oxide layer and forms a polycrystalline silicon extension section; each polycrystalline silicon extension section is connected to the same metal bus through contact holes, and the metal bus leads out a gate linear; and the width of each polycrystalline silicon extension section is smaller than or equal to the width of the corresponding N-type film to allow hole defects of each polycrystalline silicon extension section and each P-type film to be staggered on the positions. The present invention further discloses the manufacturing method of the planar gate groove-type super junction device. The planar gate groove-type super junction device and the manufacturing method thereof avoid the problem of the short circuit of the gate source caused by the polycrystalline silicon residual appeared in each hole defect when each polycrystalline silicon extension section spans each P-type film and the problem of the reduced reliability caused by each hole defect itself.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a plane gate trench type super junction device. The invention also relates to a method for manufacturing a planar gate trench type super junction device Background technique [0002] The super junction is composed of alternately arranged P-type thin layers (also called P-type pillars) and N-type thin layers (also called N-type pillars) formed in a semiconductor substrate, and the matching is completed by using P-type thin layers and N-type thin layers The formed depletion layer improves the reverse withstand voltage while maintaining a small on-resistance. [0003] The pillar structure of the PN interval of the super junction is the biggest feature of the super junction. Currently, there are mainly two methods for manufacturing the pillar structure of the PN spacer, one is obtained by multiple epitaxy and ion implantation, and the other is made by d...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/423H01L29/06H01L29/78H01L21/336
CPCH01L29/0634H01L29/4238H01L29/66477H01L29/78
Inventor 李昊
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP