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Insulated gate bipolar transistor and construction method thereof

A bipolar transistor and construction method technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components and other directions, can solve the problems of increased process cost, difficulty in collaborative optimization, and complex device manufacturing process, and achieves low implementation difficulty. , Great promotion value, the effect of reducing process cost

Active Publication Date: 2017-05-17
ZHUZHOU CRRC TIMES SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] Generally, the introduction of the "well" structure makes the manufacturing process of the device complicated, requiring multiple doping processes
In addition, the collaborative optimization of multiple doping is very difficult, and the overall process cost is significantly increased

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  • Insulated gate bipolar transistor and construction method thereof
  • Insulated gate bipolar transistor and construction method thereof
  • Insulated gate bipolar transistor and construction method thereof

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Embodiment Construction

[0034] The implementation of the present invention will be described in detail below in conjunction with the accompanying drawings and examples, so that implementers of the present invention can fully understand how the present invention uses technical means to solve technical problems, and achieve the realization process of technical effects and according to the above-mentioned realization process The present invention is implemented concretely. It should be noted that, as long as there is no conflict, each embodiment and each feature in each embodiment of the present invention can be combined with each other, and the formed technical solutions are all within the protection scope of the present invention.

[0035] The N-well structure can effectively reduce the on-state voltage drop (power consumption) of the trench gate IGBT, especially the high-concentration N-well structure. However, the high-concentration N well will sacrifice the withstand voltage performance of the devi...

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Abstract

The invention discloses an insulated gate bipolar transistor construction method. The method comprises the steps of constructing a P type diffusion area on a substrate by using P type diffusion process such that the junction depth of the P type diffusion process is larger than or equal to the depth of the trench of a transistor, a step of making a trench gate structure, a step of making an N+ source electrode area, a step of etching an emitter metal contact window, a step of allowing the P type diffusion area with a specific depth to be inverted by using high energy ions and thus constructing an N well layer in the P type diffusion area, wherein the P type diffusion area is divided by the N well layer to be upper and lower mutually isolated parts, the upper part is a P- base area, and the lower part is a P well layer, and a step of implementing a follow-up process to complete the construction of the transistor. Compared with the prior art, the method of the invention has the advantages that the technological process is greatly simplified, and thus the overall process cost and the process difficulty are reduced. At the same time, each step of the invention can be completed by adopting the prior art, and the adding of new process equipment is not needed.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to an insulated gate bipolar transistor and a construction method thereof. Background technique [0002] With the continuous development of semiconductor technology, the application of insulated gate bipolar transistor (IGBT) is more and more extensive. In the prior art, in order to optimize the on-state voltage drop and turn-off loss of the IGBT and reduce the power consumption of the device, a carrier storage layer (hole blocking layer) structure is generally used, also known as N-enhancement Layer and N-enhancement Layer. Carrier Storage N Layer). By setting an N well (carrier storage layer) under the P-base region to surround the P-base region, a hole barrier is formed there to block the holes from being extracted by the emitter electrode in the on-state, And increase the electron injection of the emitter, thereby enhancing the conductance modulation effect at this plac...

Claims

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Application Information

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IPC IPC(8): H01L29/739H01L21/331
CPCH01L29/66325H01L29/7393
Inventor 刘国友覃荣震黄建伟张泉朱利恒戴小平
Owner ZHUZHOU CRRC TIMES SEMICON CO LTD