Preparation method of heterogeneous GaAs-Ge-GaAs pin diode for multi-layer holographic antenna
A gaas-ge-gaas, heterogeneous structure technology, which is applied in the directions of devices, antennas, and antenna components that make antennas work in different bands at the same time, and can solve the problems of poor controllability of solid-state plasma concentration and distribution, injection dose and energy Large, incompatibility and other problems, to achieve the effect of increasing solid-state plasma concentration, increasing breakdown voltage, and increasing carrier lifetime
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Embodiment 1
[0066] An embodiment of the present invention provides a method for preparing a pin diode of a GaAs-Ge-GaAs heterostructure for a multilayer holographic antenna. The pin diode is used to manufacture a reconfigurable multilayer holographic antenna (1). Please refer to figure 1 , figure 1 A schematic structural diagram of a reconfigurable multi-layer holographic antenna provided by an embodiment of the present invention. The holographic antenna (1) includes a semiconductor substrate (11), an antenna module (13), a first holographic ring (15) and a second holographic ring (17); the antenna module (13), the first A holographic ring (15) and the second holographic ring (17) are fabricated on the semiconductor substrate (11) by semiconductor technology; wherein, the antenna module (13), the first holographic ring Both the ring (15) and the second holographic ring (17) include pin diode strings connected in series;
[0067] Please refer to figure 2 , figure 2 A schematic diagra...
Embodiment 2
[0123] See Figure 8a-Figure 8r , Figure 8a-Figure 8r It is a schematic diagram of another manufacturing method of a GaAs-Ge-GaAs heterostructure pin diode used in a reconfigurable multilayer holographic antenna provided by an embodiment of the present invention. On the basis of the first embodiment above, the preparation of a GaAs-Ge-GaAs heterostructure pin diode with a channel length of 22nm (solid-state plasma region length of 100 microns) is taken as an example to describe in detail, and the specific steps are as follows:
[0124] Step 1, substrate material preparation steps:
[0125] (1a) if Figure 8a As shown, the (100) crystal orientation is selected, the doping type is p-type, and the doping concentration is 10 14 cm -3 A GeOI substrate sheet 101, the thickness of the top layer Ge is 50 μm;
[0126] (1b) if Figure 8b As shown, the method of chemical vapor deposition (Chemical vapor deposition, referred to as CVD) is used to deposit a layer of the first SiO wi...
Embodiment 3
[0154] Please refer to Figure 9 , Figure 9 A schematic structural diagram of another GaAs-Ge-GaAs heterostructure pin diode provided by an embodiment of the present invention. The GaAs-Ge-GaAs heterostructure pin diode adopts the above-mentioned as figure 2 The preparation method shown is made, specifically, the pin diode of the GaAs-Ge-GaAs heterostructure is prepared and formed on the GeOI substrate 301, and the P region 304, the N region 305 of the pin diode and the lateral position of the P region 304 The i region (intrinsic region) between the N region 305 is located in the top layer Ge302 of the GeOI substrate. Wherein, the pin diode can be isolated by STI deep trenches, that is, an isolation trench 303 is provided outside the P region 304 and the N region 305, and the depth of the isolation trench 303 is greater than or equal to the thickness of the top layer Ge302.
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