Bare chip structure applied to testing and manufacturing method thereof

Abstract

The invention discloses a bare chip structure applied to testing and a manufacturing method thereof. The bare chip structure 100 comprises a main PCB (Printed Circuit Board) 101, a subsidiary PCB 102, a bare chip 103, bonding pads 104 / 106, bonding wires 105 / 107, a gasket 110, metal header pins 111, a protection cover 112 and electrical insulating oil 114, and is characterized in that the gasket 110 is pasted on the main PCB 101, and the bare chip 103 is pasted on the gasket 110; the bonding pads 104 surround the bare chip 103, are arranged on the main PCB 101 and are connected with a metal PAD of the bare chip 103 through the bonding wires 105; the subsidiary PCB 102 is located at the periphery of the bonding pads and pasted on the main PCB 101, and realizes electrical connection with the main PCB 101 through the metal pins 111; the bonding pads 106 are arranged on the subsidiary PCB 102 and connected with the metal PAD of the bare chip 103 through the bonding wires 107; and the protection cover 112 is pasted on the main PCB 101, and the electrical insulating oil 114 is injected into the protection cover 112. In the invention, the structure is of a high-low-high step shape, the density of bonding wires in unit area is improved, the metal PAD can be ensured not to be polluted when the bare chip is pasted, and the bare chip and the bonding wires are avoided from being oxidized in the air.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuit testing, and relates to a connection and protection structure between a bare chip and a printed circuit board and a manufacturing method thereof. Background technique [0002] After the chip tape-out is completed, the bare chip is generally packaged in plastic or ceramic materials to provide environmental protection, and then various functional tests can be performed. The packaging cycle takes up valuable testing time and slows down the pace of product marketization. Therefore, testing bare chips has become a hot spot in international research. [0003] Wafer-level testing can test bare chips through wafer probes and special test benches, but it can only complete relatively simple test tasks, and has more limitations in testing the actual functions of chips; some foreign companies have launched KGD ( Known Good Die) bare chip products, using special fixtures to test bare ...

AI Technical Summary

Problems solved by technology

[0003] Wafer-level testing can test bare chips through wafer probes and special test benches, but it can only complete relatively simple test tasks, and has more limitations in testing the actual functions of chips; some foreign companies have launched KGD ( Known Good Die) bare chip products, using special fixtures to test bare chips, the special customization of fixtures and development cycle still cannot meet the timeliness requirements of chip testing; at present, it is more common to fix the bare chip on the PCB board, Use a bonding machine to connect the chip pins and PCB board pads, and then use special glue to cover and protect the entire structure, so that the chip can be fully functionally tested in the laboratory environment

However, once the glue is cured, it is difficult to remove from the bare core, and the maintainability is not good, and the process of covering the bare chip with the glue may cause contact and connection between the bonding wires, resulting in poor reliability.

With the increasing complexity of chips and hundreds of functional pins, it is necessary to process the same number of bonding pads on the PCB as bonding points. Due to the length requirements of bonding wires, metal bonding soldering The disk area and spacing are limited, and it is very easy to cause contact connection between the bonding wires during bonding. The requirements for the processing accuracy of the PCB board and the technical level of the bonding operator are high, and multi-pin bare chips can be realized under ordinary laboratory conditions. It is more difficult to effectively connect with the PCB board; and the larger the area of ​​the bare chip, the more conductive glue is required for bonding on the PCB board. When the bare chip is pressed on the PCB board, the conductive glue will be on the bare chip. The overflow on the side is very easy to adhere to the metal pad of the bare chip, forming a short circuit between the metal pads, causing the bare chip to be scrapped

Images