Capacitance charge-discharge structure-based serial PWM signal decoding circuit and method

Abstract

The invention provides a capacitance charge-discharge structure-based serial PWM signal decoding circuit. The circuit comprises a time sequence logic generation circuit and at least two capacitance charge-discharge decoding modules, wherein the input end of the time sequence logic generation circuit receives a PWM differential signal, and the time sequence logic generation circuit generates a time sequence logic signal; the input ends of the capacitance charge-discharge decoding modules are connected with the output end of the time sequence logic generation circuit, and the capacitance charge-discharge decoding modules perform charge-discharge according to the time sequence logic signal; and in a decoding process, a voltage, before charge-discharge, of charge-discharge capacitance of each capacitance charge-discharge decoding module is a common mode voltage VCM, a voltage, after charge-discharge, of a charge-discharge node is VC, and the PWM signal is identified by judging voltage difference polarity of the two voltages, so that decoding is realized. The invention furthermore provides a capacitance charge-discharge structure-based serial PWM signal decoding method. According to the circuit and the method, the structure is simple; no synchronous code stream is required; the use of a complex CDR and an oversampling structure is avoided; the PWM signal decoding under different rates is realized; the signal transmission efficiency is improved; and the power consumption is reduced.

Description

technical field [0001] The invention relates to the field of integrated circuit design related to the M-PHY interface, in particular to a serial PWM signal decoding circuit and method based on a capacitor charging and discharging structure. Background technique [0002] In the field of serial interfaces, PWM signals are often used for data transmission in low-speed mode, such as mipi M_PHY, which is characterized by the fact that the low level time in a UI accounts for 1 / 3, and the high level accounts for 2 / 3 to represent data. 1. The low level time accounts for 2 / 3, and the high level accounts for 1 / 3 to represent data 0. Its transmission data rate ranges from a few megahertz to hundreds of megahertz to meet the needs of saving power consumption under different data transmission volumes, and at the same time, there are cases where no synchronization code is sent in low-speed mode. [0003] At present, the existing schemes adopt oversampling, or realize the decoding of seri...

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Problems solved by technology

[0003] At present, the existing schemes adopt oversampling, or realize the decoding of serial PWM signals based on the CDR structure, but all of them have complex circuit structures, waste redundant power consumption, cannot cover the large data rate variation range, and even need to cooperate with the synchronization code to realize decoding. Therefore, there is an urgent need for a PWM signal receiving circuit that has a simple structure, low power consumption, adapts to different operating rates, and can realize reception without synchronous data codes.

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