Fin-type semiconductor device forming method

Abstract

A method for forming a fin-type semiconductor device, comprising: providing a substrate including a circuit area and a storage area, the substrate surfaces of the circuit area and the storage area respectively have fins; forming an isolation layer on the surface of the substrate, the surface of the isolation layer is lower than The top surface of the fin; a dielectric layer is formed on the isolation layer and the surface of the fin, and the dielectric layer in the storage area has a first trench across the fin, and the first trench exposes part of the sidewall and top of the fin in the storage area On the surface, there is a second trench across the fin in the dielectric layer of the circuit area, and the second trench exposes part of the sidewall and top of the fin in the circuit area; on the sidewall and top of the fin at the bottom of the first trench forming a first gate dielectric layer; forming a second gate dielectric layer on the sidewalls and tops of the fins at the bottom of the second trench and on the surface of the first gate dielectric layer; and then forming a first gate in the first trench, A second gate is formed in the second trench. The leakage current in the fin semiconductor device is reduced, and the stability of the fin semiconductor device is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a fin-type semiconductor device. Background technique [0002] Static Random Access Memory (SRAM), as a member of memory, has the advantages of high speed, low power consumption and compatibility with standard processes, and is widely used in computers, personal communications, consumer electronics (smart cards, digital cameras, Multimedia player) and other fields. [0003] figure 1 It is a schematic diagram of the circuit structure of the storage unit of the SRAM with the existing 6T (Transistor, transistor) structure, including: the first PMOS transistor P1, the second PMOS transistor P2, the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3 and fourth NMOS transistor N4. Wherein, the first PMOS transistor P1, the second PMOS transistor P2, the first NMOS transistor N1, and the second NMOS transisto...

AI Technical Summary

Problems solved by technology

[0006] However, as the device density in the SRAM increases and the size shrinks, the performance of the SRAM composed of FinFETs also decreases.

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