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A scan chain-based chip analysis method

An analysis method and scan chain technology, applied in the field of information electronic chip design, to achieve the effect of improving development efficiency

Active Publication Date: 2020-12-18
RAMAXEL TECH SHENZHEN
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Existing JTAG tools cannot meet this requirement well for existing chip designs

Method used

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  • A scan chain-based chip analysis method
  • A scan chain-based chip analysis method
  • A scan chain-based chip analysis method

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Embodiment Construction

[0011] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0012] figure 1 It is a schematic diagram of a register with scan input; the register with scan input adds a data selector MUX before the data input port of the general register FF, and the data selector MUX includes a data input port Data, a scan input port ScanIn and a scan enable control port Scan Enable; The register with scan input also includes a clock input port Clk, a data output port Q and a scan output port Scan Out.

[0013] figure 2 It is a schematic...

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Abstract

The invention provides a scan chain-based chip analysis method which is characterized in that common registers requiring state storage in a CPU are replaced by scan-in registers; when an exception occurs in the CPU, a JTAG outputs a serial scan triggering command, and scan chain data storage operations are started; data serials of the scan-in registers are output to a debugging host via a JTAEK port; a debugger analyzes data of each scan-in register received by the debugging host; after analysis is over, the JATG is controlled to output a control resetting signal to perform a resetting operation on the CPU and control the CPU to restore normal work. Via the scan chain mechanism, the states of main registers of chips can be read out rapidly and conveniently when an exception occurs in a CPU; with the additional assistance of JTAG tools, rapid analysis and fault location can be performed on the CPU with the exception, so that the development efficiency can be improved greatly.

Description

technical field [0001] The invention relates to the field of information electronic chip design, in particular to a scan chain-based chip analysis method. Background technique [0002] In the development process of embedded products, software design and debugging is an important link in the research and development. Any software needs to be debugged many times before it is finalized. In order to improve design efficiency, many chip design companies have simultaneously designed software debugging tools. All kinds of debugging tools are basically similar to communicating and controlling directly with the CPU through the JTAG (an international standard test protocol, mainly used for chip internal testing) port to control the execution of the program. For example, single-step debugging. A prerequisite for this type of debugging is that the CPU itself is working normally. If there is a problem or abnormality in the CPU itself, the state of various software or the CPU will be los...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/22G06F11/263
CPCG06F11/2236G06F11/2635
Inventor 赵胜平
Owner RAMAXEL TECH SHENZHEN