14 results about "Microchip Analysis" patented technology

The invention provides a high-entropy nano enzyme. The chemical formula of the high-entropy nano enzyme is Mn < 0.4 > Co < 0.4 > Ni < 0.4 > Cu < 0.4 > Zn < 0.4 > Fe < 2.0 >) O. The invention also provides a preparation method of the high-entropy nano-enzyme, which comprises the following steps: dissolving manganese nitrate tetrahydrate, cobalt nitrate hexahydrate, nickel nitrate hexahydrate, copper nitrate trihydrate, zinc nitrate hexahydrate and sodium citrate in deionized water to prepare a clear solution A; dissolving potassium ferricyanide in deionized water to prepare a clear solution B; directly pouring the solution B into the solution A, stirring, standing and aging the obtained mixed solution at room temperature, and centrifugally collecting a product; and calcining the sample powder in a muffle furnace to obtain the high-entropy nano-enzyme. The invention further provides a catalyst which is composed of the high-entropy nano enzyme, 3, 3 ', 5, 5'-tetramethyl benzidine and H2O2. The invention also provides a method for detecting reduced glutathione by using the microfluidic paper chip analysis device. The invention provides a new normal form for constructing a multifunctional biosensing and environment monitoring platform.

A chip binning system includes a chip analysis database and a chip binning server communicatively connected to each other. The chip binning server includes a feature generation module, a first binning module, a second binning module, and a bin reduction module. The feature generation module generates chip feature data according to the chip analysis data. The first binning module generates chip performance levels according to the chip feature data, and performs a first binning on the chips according to the chip performance levels to generate first binning data. The second binning module performs a second binning on the chips in each bin in the first binning data according to chip power levels in the chip analysis data to generate second binning data. The bin reduction module performs a binning reduction on a number of bins in the second bin data to generate third binning data.

The invention relates to an analysis method and device for a chip. The method comprises the steps that data capture is conducted on latest results of a target chip by different analysis tools to obtain target data, the number of the analysis tools is at least two, and analysis conducted on the target chip by the analysis tools is different; taking the target data corresponding to each analysis tool as an analysis basis and sending the analysis basis to other analysis tools; performing anomaly evaluation based on the target data to obtain an evaluation result; under the condition that the evaluation result is abnormal, the abnormal evaluation result serves as an analysis basis for optimization and is sent to a first tool in the analysis tools, and all the analysis tools are controlled to end analysis until an end condition is met; the end condition is that the evaluation result is normal. The accuracy and speed of chip analysis are remarkably improved, multi-dimensional linkage analysis is achieved, and the method is suitable for multiple research and development stages of chip development and wide in application range.

The invention relates to a manual noise reduction intelligent door and window system, and belongs to the technical field of intelligent doors and windows. The manual noise reduction intelligent door and window system comprises an outer frame, a window sash is hinged to the inner side of the outer frame, a positioning groove is formed in the surface of the window sash, and an intelligent noise reduction mechanism connected with the positioning groove in a clamped mode is installed in the outer frame in an embedded mode; the intelligent noise reduction mechanism comprises an annular frame embedded in the inner side of the outer frame, and an annular groove communicating with the positioning groove is formed in the inner side of the annular frame; external noise is collected in real time through the microphone, a built-in AI chip of the Internet of Things microcontroller analyzes noise spectrum and phase and generates reverse interference sound, and the loudspeaker emits sound waves to the noise direction for interference offset, so that structural sound transmission caused by vibration is effectively inhibited, and the problem that the resonance efficiency of an existing door and window sound barrier is remarkably reduced is solved. And the active noise reduction capability is improved.

The present application belongs to the field of umbrella, and particularly relates to a self-adjusting intelligent sunny and rainy umbrella based on hybrid energy technology, which comprises a sunny and rainy umbrella body, the sunny and rainy umbrella body comprising a sunny and rainy umbrella stick, a sunny and rainy umbrella rib and a sunny and rainy umbrella surface, the inner side of the sunny and rainy umbrella surface being provided with a piezoelectric patch, the piezoelectric patch generating electric energy through deformation, a storage battery being arranged on the sunny and rainy umbrella body, and the storage battery storing the electric energy generated by the piezoelectric patch. According to the piezoelectric effect, the piezoelectric patch is used to collect rainwater vibration energy, unstable current is adjusted to be relatively stable current in an energy adjusting chip, and the grade of rainfall at this time can be judged according to the size of the current in an energy analysis chip. According to the rainfall intensity and the angle of oblique wind and rain, the intensity of ultraviolet rays and the angle of solar radiation obtained by the energy analysis chip, the umbrella surface telescopic assembly is intelligently adjusted, and the appearance of the sunny and rainy umbrella is changed to achieve the functions of sun-shading and rain-avoiding.

The application aims to provide a power network reserved low-layer metal wiring resource alleviating on-chip voltage drop method, which comprises the following steps: reserving a deployment area of a low-layer metal resource in a chip layout stage; correcting the deployment area; and using the metal resource in the deployment area according to chip analysis results after wiring is completed. In the layout and wiring and clock tree synthesis stages, the low-layer metal wiring resource is reserved for connecting the power supply tracks of adjacent standard cells, so that the problem of excessive voltage drop caused by excessive low-layer metal resistance can be effectively alleviated by flexibly enabling the reserved wiring resource in the late stage of chip design.

This disclosure provides an artificial intelligence (AI) flash and a method for adjusting its parameters. The AI ​​flash can capture images via its onboard camera or sensor, and / or receive images captured by other devices. The AI ​​flash can receive images from cameras, mobile phones, smart glasses, or any other device capable of capturing images. The AI ​​flash can receive images via Wi-Fi, 2.4 GHz, P2P, Bluetooth, HDMI, and / or proprietary protocols provided by the AI ​​flash manufacturer (or protocols customized for a specific AI flash type). The AI ​​flash can analyze the image using an AI chip and determine how to adjust its parameters based on the analysis results. The AI ​​flash can adjust its parameters accordingly and output light based on the adjusted parameters. This achieves the desired shooting or lighting effect.

The invention discloses a data protection method and system based on a USB flash disk, and relates to the technical field of data protection, and the method specifically comprises the steps of S100 state monitoring and dormancy triggering, S200 physical level connection disconnection, S300 dynamic threat perception, S400 intelligent locking decision and execution, and S500 security verification and state recovery. Dormancy is triggered after idle timeout; the power management module is used for controlling the physical switch to cut off the electrical connection between the storage chip and the interface module to enter a low-power-consumption state; physical movement data and peripheral equipment information are collected through the sensor module in the dormancy period; the main control chip analyzes the environment data and triggers encryption locking if a locking condition is met; and when recovery is carried out, reconnection can be carried out through dual verification including a static PIN code and a dynamic token, and through a physical-level connection disconnection mechanism, the storage chip is isolated and an illegal access path is blocked during dormancy, so that the defects of a traditional scheme in the aspects of physical isolation and dynamic protection are overcome.

An indoor waste gas detection device disclosed by the present invention comprises a detection box, the detection box is internally provided with a detection element and an exhaust funnel, the bottom of the exhaust funnel is sequentially provided with an airflow trend assembly and a processing mechanism, an air inlet fan sucks indoor air from a top grid through negative pressure, and the indoor air is stably conveyed to the exhaust funnel after primary filtration. A built-in multi-sensor array synchronously detects gas components, data are uploaded to a main control chip for analysis in real time, when the concentration of pollutants does not exceed the standard, a control column rotates to enable a gas flow groove to be aligned with an exhaust connecting pipe, gas is directly exhausted, once formaldehyde or TVOC and the like are recognized to exceed the standard, the control column switches a channel, and activated carbon preferentially captures organic pollutants in an adsorption box, so that the adsorption effect is achieved. And then the gas rises to the spraying area, atomized liquid drops sprayed by the water storage cover dissolve residual acidic substances and soluble organic matters, purified clean air is discharged from the side wall, and spraying wastewater is precipitated and then sent back to the water storage cover by a circulating pump to realize liquid reuse.

The application discloses a high-precision semiconductor test sorting method and equipment, and belongs to the technical field of semiconductor testing, and comprises the following steps: executing a test process of a target chip, recording a target marking chip which is qualified in the test as a target marking chip, analyzing a laser marking energy fluctuation characteristic parameter, determining a first execution path of a laser marking system, combining the laser marking energy fluctuation characteristic parameter to execute adaptive adjustment of the laser marking system, analyzing a second execution path of the laser marking system after the adjustment is completed, analyzing a laser marking carbonization characteristic parameter, and determining a third execution path of the laser marking system. The application can realize real-time monitoring and dynamic adjustment of energy fluctuation and carbonization quality in the laser marking process, not only improves the response speed and regulation and control precision of marking abnormalities, but also effectively avoids the misjudgment or good product NG problem caused by laser parameter drift, so that the stability, yield and automation level of the whole machine test sorting process are significantly enhanced.

The invention relates to an autonomous hair clipper based on artificial intelligence. The autonomous hair clipper mainly comprises a hair clipper body, a hair cutting method and a terminal. The hair clipper comprises a high-precision camera, a high-precision sensor, an intelligent control system, a flexible blade and a self-adaptive clamping mechanism. The high-precision camera and the sensor are arranged at the front end of the hair clipper and used for collecting data such as hair length, density and facial contour; the intelligent control system is internally provided with a high-performance processor and an Al chip and is used for analyzing head shape characteristics of a user, recommending a haircut scheme and controlling the self-adaptive clamping mechanism to realize precise trimming; the flexible blade and the self-adaptive clamping mechanism are made of flexible materials, and the self-adaptive clamping mechanism can flexibly adjust the trimming angle and length according to the change of the head shape. The hairdressing method comprises the steps of user head shape recognition, personalized scheme recommendation and intelligent execution. The terminal supports an iOS, an Android and a PC terminal, provides a user interface, and allows input of preference information, viewing of a haircut scheme preview, remote control of the haircut device and receiving of real-time feedback in the haircut process.

The application provides a method for random stroboscopic coordination and synchronization of multiple dimming chips in a same light device, comprising: each dimming chip receiving a random number array input by a master controller; each dimming chip analyzing a light channel brightness value set input and outputting a control signal to control light source brightness; and each dimming chip indexing a starting number in the random number array according to an obtained asynchronous stroboscopic starting random number, starting countdown stroboscopic, to complete a current stroboscopic period. In the application, because the random number array, asynchronous stroboscopic starting random number, analyzed light channel brightness value set and stroboscopic period received by each dimming chip in the same light device from the same master controller are consistent, the stroboscopic of each light source in the light device is ensured to be consistent, and each stroboscopic period will change with the corresponding starting number to form asynchronous stroboscopic or random stroboscopic effect.

This invention discloses a simulation system and method for transient radiation effect behavior-level fault injection based on SiP chips, belonging to the field of chip analysis technology. The simulation system includes an ADC simulation module, a DAC simulation module, an FPGA simulation module, a voltage comparator simulation module, a level driver simulation module, a signal generation module, and a fault injection module. The output of the signal generation module is connected to the inputs of the ADC, voltage comparator, FPGA, and DAC simulation modules. The outputs of the ADC and voltage comparator simulation modules are connected to the input of the FPGA simulation module. The output of the FPGA simulation module is connected to the inputs of the DAC and level driver simulation modules. The output of the fault injection module is connected to the input of the fault injection target module. This invention provides a fast and accurate simulation system and method for studying the transient dose rate effect of SiP chips, and is a useful supplement to the experimental study of SiP using transient radiation effects.

The application discloses a chip failure analysis method and related equipment, the method comprises the following steps: analyzing the multi-modal data of the chip to be analyzed to obtain an initial failure characterization set; based on the initial failure characterization set, strategy reasoning is performed in the pre-constructed failure knowledge graph to obtain the target analysis strategy of the chip to be analyzed at present, and then the new failure characterization is determined; the initial failure characterization set and the failure knowledge graph are updated based on the new failure characterization, and the strategy reasoning step is iteratively executed until the preset convergence condition is met; when the preset convergence condition is met, the probability values of the failure mode and the root cause are calculated based on all the failure characterizations in the updated failure characterization set; based on the probability values and the updated failure knowledge graph, reverse root cause reasoning is performed to obtain the root cause of the failure of the chip to be analyzed. The application can dynamically adjust the analysis strategy according to the actual failure characterization of the chip, and improves the efficiency and accuracy of chip failure analysis, and can be widely applied in the field of chip analysis technology.