Semiconductor wafer, semiconductor structure and method of manufacturing semiconductor wafer
A technology of semiconductors and wafers, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., and can solve problems such as damage to semiconductor wafers
Active Publication Date: 2020-03-03
SAMSUNG ELECTRONICS CO LTD
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- Application Information
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Problems solved by technology
When the process temperature increases, a large amount of heat may be applied to the semiconductor wafer, and thus the semiconductor wafer may be damaged
Method used
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Embodiment Construction
[0018] figure 1 is a plan view showing a semiconductor wafer 100 according to an embodiment of the present disclosure. figure 2 is shown taken along line II-II' figure 1 A cross-sectional view of a semiconductor wafer 100. image 3 is shown taken along line III-III' figure 1 A cross-sectional view of a semiconductor wafer 100.
[0019] refer to Figures 1 to 3 , the semiconductor wafer 100 may include a body 100 , a notch 120 , and first and second bevel regions 130 and 140 .
[0020] The semiconductor wafer 100 may be a silicon wafer, or may include a semiconductor element such as germanium (Ge) or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). . Furthermore, the semiconductor wafer 100 may be silicon-on-insulator.
[0021] The body 110 may determine the overall shape of the semiconductor wafer 100 . The body 110 may include a chip formation region 111 in which passive devices, acti...
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Abstract
The invention discloses a semiconductor wafer, a semiconductor structure and a method for manufacturing the semiconductor wafer. The semiconductor wafer includes: a main body including first and second surfaces facing each other; a recess including a depression on the outer periphery; a first chamfered region formed along the outer periphery of the main body, the first chamfered region including a first slope, The first slope connects the first and second surfaces and has a first height relative to a line extending from a first point where the first surface and the first slope meet to a second point where the second surface and the first slope meet; or a second chamfered area contacted by the opening, the second chamfered area includes a second slope connecting the first and second surfaces and relative to the second surface from a third point where the first surface and the second slope meet A straight line extending from a fourth point meeting the second slope has a second height different from the first height.
Description
technical field [0001] Example embodiments of inventive concepts relate to semiconductor wafers, semiconductor structures, and / or methods of manufacturing semiconductor wafers. Background technique [0002] Due to microfabrication and complication regarding semiconductor circuits, the process of manufacturing a semiconductor device may be performed at a relatively high temperature, which results in a reduction in its design rules. When the process temperature increases, a large amount of heat may be applied to the semiconductor wafer, and thus the semiconductor wafer may be damaged. [0003] Meanwhile, the notch may be mainly used to indicate a crystal orientation of a semiconductor wafer having a diameter of 300 μm or more, and the notch may be used to align the semiconductor wafer during a semiconductor manufacturing process. Contents of the invention [0004] Example embodiments of the inventive concepts provide a semiconductor wafer configured to reduce (or alternativ...
Claims
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IPC IPC(8): H01L21/02H01L23/544
CPCH01L21/02013H01L21/02021H01L23/544H01L2223/54493H01L2223/54426H01L22/12H01L21/02035H01L21/0262H01L21/324H01L23/562
Inventor 金钟洙崔三宗金秀莲具泰亨朱炫姬金清俊俞智原
Owner SAMSUNG ELECTRONICS CO LTD