Voltage-aware adaptive static random access memory (SRAM) write assist circuit

Abstract

Approaches for a write assist circuit are provided. The write assist circuit includes a plurality of binary weighted boost capacitors which each contain a first node coupled to a bitline and a second node connected to a corresponding boost enabling transistor, and a plurality of boost enabling transistors which each contain a gate connected to a boost control enable signal for controlling a corresponding binary weighted boost capacitor. The boost control enable signal of each of the plurality of boost enabling transistors is controlled by encoded values based on a power supply level.

Description

technical field [0001] The invention relates to a static random access memory (static random access memory; SRAM) writing auxiliary circuit, in particular to an SRAM writing auxiliary circuit and a method thereof which adapt to voltage changes and are independent of process and temperature changes. Background technique [0002] Memory devices are commonly used as internal storage areas in computing devices or other electronic devices. One particular type of memory used to store data in computing devices is random access memory (RAM). RAM is commonly used as main memory in computing environments and is usually volatile in that all data stored in the RAM is lost once the power is turned off. [0003] Static RAM (SRAM) is an example of RAM. SRAM has the advantage of retaining data without needing to be refreshed. A typical SRAM device includes an array of individual SRAM cells. Each SRAM cell is capable of storing a binary voltage value representing a logical data bit (eg, ...

AI Technical Summary

Problems solved by technology

In particular, as the operating voltage of an integrated circuit decreases as the size of the circuit shrinks, the read and write margin of the SRAM cell (which measures the reliability of the bits that can be read and written to the SRAM cell) decreases.

Reduced read and write margins can thus lead to errors in the corresponding read and write operations of the SRAM cell

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