Hafnium oxide based ferroelectric grid structure and preparation technology thereof

Abstract

The invention discloses a hafnium oxide based ferroelectric grid structure. The structure comprises a substrate, and a buffer layer, a bottom electrode layer, a ferroelectric layer and a top electrode layer are laminated on the surface of the substrate successively, and the material of the ferroelectric layer comprises hafnium oxide. The invention also discloses a preparation technology of the hafnium oxide based ferroelectric grid structure. The hafnium oxide based ferroelectric grid structure has high electrical performances, the vertical size of the whole storage medium of a ferroelectric memory is reduced by 10 to 20 times, and the structure and technology are compatible with the silicon technology.

Description

technical field [0001] The invention relates to a memory, in particular to a ferroelectric gate structure based on hafnium oxide and a preparation process thereof. Background technique [0002] Ferroelectric memory (FRAM) has been widely studied because of its high speed, non-volatility, low operating voltage, strong radiation resistance, and compatibility with standard silicon integrated circuit technology. Among them, the gate electrode / ferroelectric layer / buffer layer / substrate (MFIS) structure ferroelectric field effect transistor has become a research hotspot in the field of FRAM because of its non-destructive readout, simple structure and high storage density. However, in the MFIS structure, the dielectric constant and thickness of the I layer are required to be high, and when the dielectric constant of the buffer layer is small, the structure will cause most of the voltage to fall on the buffer layer, resulting in the failure of the ferroelectric layer to separate. L...

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Problems solved by technology

[0005] First, due to the mutual reaction and mutual diffusion between the ferroelectric film and the silicon substrate, it is difficult to form a good interface state between the ferroelectric film and the silicon substrate. The usual solution is to introduce A buffer layer is used to improve the interface performance, but the buffer layer currently studied has a huge difference in dielectric constant and thickness from the ferroelectric layer, and the partial voltage is large during the signal erasing and writing process, resulting in a lower operating voltage of the ferroelectric layer. It cannot be completely flipped, and the storage window is small, which means that a larger voltage needs to be applied to completely flip the ferroelectric layer, increasing the operating voltage

[0006] Second, most of the traditional ferroelectric materials currently used in memory, such as SBT, PZT, BTO, etc., still have many problems in the semiconductor process, such as incompatibility with silicon processes, lead pollution caused by PZT films, small energy bands and A relatively large physical thickness (usually hundreds of nanometers) is required to obtain a large remanent polarization value, which hinders the development of miniaturization of memory devices

[0007] Thirdly, the MFIS structure ferroelectric field effect transistor is currently a research hotspot because of its simple structure and high storage density. Interface effect, making storage performance worse

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