Structure of coreless substrate and manufacturing method thereof

Abstract

The embodiment of the invention provides a manufacturing method of a coreless substrate. The method includes: forming a first conductive line on a first copper foil; laminating a first prepreg and a second copper foil on the first conductive line through a first lamination process; forming a second conductive line by employing the second copper foil; laminating a second prepreg and a third copper foil on the second conductive line through a second lamination process; removing the first copper foil and the third copper foil and performing drilling to form one or more first blind holes from the external surface of the second prepreg to the second conductive line and one or more second blind holes from the first conductive line to the second conductive line; and filling in the blind holes and forming a third conductive line on the second prepreg.

Description

technical field [0001] The invention relates to the field of semiconductor packaging, in particular to a structure of a coreless substrate and a manufacturing method thereof. Background technique [0002] In order to meet the increasingly miniaturized, intelligent, high-performance and high-reliability development of electronic products, the miniaturization and intelligence of chips have led to an increase in the number of chip package pins, and the size of package pins is also rapidly increasing. At the same time, SiP (System In a Package) requires multiple active electronic components with different functions and optional passive devices to be packaged into a functional system, which proposes the realization of multiple Packaging requirements for a high-performance chip. [0003] When the chip pad spacing of the chip is less than 50 μm, the package must adopt BOT (Bump on Trace) technology to directly bond the copper pillar bumps on the chip surface to the fine circuit of...

AI Technical Summary

Problems solved by technology

The reason for forming a three-layer substrate with an asymmetric structure is mainly that the high-temperature curing time and conditions of each layer of resin are different, forming different internal stresses, resulting in the overall structure being asymmetrical in terms of mechanics, with high cost and high warpage degree of question

During the process, the formed substrate has high warpage, which has a great impact on the subsequent packaging, especially for the flip-chip welding technology commonly used in high-end packaging. The ball cannot be bonded, resulting in failure; or even if it is barely bonded, there will be a large stress between the chip and the substrate, resulting in poor reliability of the package, poor mechanical and thermal performance, resulting in solder ball breakage during use, resulting in failure

[0005] At present, there is a technology to make a three-layer substrate starting from a layer of prepreg. Although a three-layer substrate with a symmetrical resin structure relative to the metal in the middle layer can be obtained well, since the processing starts from the prepreg, the thickness of the substrate is only 20um-40um, The board is too thin, the operation is more difficult, the process is more difficult during processing, and the expansion and contraction control of the substrate is difficult, so the processing is more difficult

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