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Stacked package structure and manufacturing method

A technology of packaging structure and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve the problems of thick stacking packaging structure, high manufacturing cost, complex process, etc., and achieves reduced thickness and reduced processing. Cost, effect of simplifying manufacturing process

Inactive Publication Date: 2017-09-12
SHUNSIN TECH (ZHONG SHAN) LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the existing stacked package structure and its manufacturing method mainly have two disadvantages: 1. The packages are directly stacked, resulting in a relatively thick stacked package structure, which cannot meet the requirements of light and thin electronic products; 2. The first package and the second package After the packages are manufactured separately, they are then stacked. The process is complicated and the manufacturing cost is high.

Method used

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  • Stacked package structure and manufacturing method
  • Stacked package structure and manufacturing method
  • Stacked package structure and manufacturing method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0056] refer to figure 1 As shown, it is a structural schematic diagram of a preferred embodiment of the package-on-package structure of the present invention.

[0057] The package-on-package structure of this embodiment includes a first package 1 and a second package 2 stacked on the first package 1, wherein:

[0058] The first package body 1 includes a substrate 1b, and the substrate 1b has two opposite sides. A first component is mounted on one side of the substrate 1b and a first pad 1g is provided, and the first component is electrically connected to the first pad 1g through a first package circuit 1e. In a specific implementation, the first component may be a first chip 1c. The other surface of the substrate 1b is provided with first solder balls 1a for electrical connection with external components. The first package body 1 further includes a first glue injection body 1d covering the first component, the first solder pad 1g and the first package circuit 1e.

[0059]...

Embodiment 2

[0065] refer to figure 2 As shown, it is a structural schematic diagram of another preferred embodiment of the package-on-package structure of the present invention.

[0066] The package-on-package structure of this embodiment includes a first package body 1 and a third package body 3 stacked on the first package body 1, wherein

[0067] The structure of the first package body 1 is the same as that in the first embodiment, and will not be repeated here.

[0068] The third package body 3 includes a passive device, a third chip 3c, a second package circuit 3b electrically connecting the passive device and the third chip 3c, covering the passive device, the third chip 3c and the second package circuit 3b The third injection colloid 3d.

[0069] The third package 3 is attached to the first package 1 through the joint of the third glue 3d and the first glue 1d, and the first package circuit 1e and the second package circuit 3b are arranged on the first package 1d. The conductiv...

Embodiment 3

[0072] refer to image 3 As shown, it is a structural schematic diagram of another preferred embodiment of the package-on-package structure of the present invention.

[0073] The package-on-package structure of this embodiment includes a first package 1 , a third package 3 stacked on the first package 1 , and a second package 2 stacked on the third package 3 . The structures of the first package body 1 , the second package body 2 , and the third package body 3 are the same as those in the first and second embodiments. The third package body 3 is stacked on the first package body 1 in the same manner as in the second embodiment. The second package body 2 is stacked on the third package body 3 through the bonding of the second glue body 2b and the third glue body 3d.

[0074] It can be understood that, in specific implementation, more layers of stacking and packaging can be performed with reference to the stacking manner of Embodiment 3 according to actual needs.

[0075] Bas...

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Abstract

The invention discloses a stacked package structure and a manufacturing method. The stacked package structure includes a first package and a second package. The first package includes a substrate, a first component mounted on the substrate, a first glue injection body covering the first component, and a first package line. The second package comprises a second component, and a second glue injection body covering the second component. The second package is attached to the first package by the engagement of the second glue injection body with the first glue injection body. The first package line and the second component are electrically connected via a conductive fill hole provided on the first glue injection body and / or the second glue injection body. The present invention discloses the stacked package structure and the manufacturing method thereof, which are designed to reduce the thickness of the stacked packaging structure, simplify the manufacturing process and reduce the processing cost.

Description

technical field [0001] The invention relates to the technical field of semiconductor device packaging, in particular to a stacked packaging structure and a manufacturing method thereof. Background technique [0002] The traditional packaging form of electronic components in electronic equipment is generally to solder multiple independently packaged components to a printed circuit board, and the electronic components are connected by wires to achieve complete functions. A plurality of independently packaged electronic components are arranged on a printed circuit board (Printed Circuit Board, PCB), which needs to occupy a large area, and a PCB with a large area will increase the size of the electronic device and increase the manufacturing cost. In order to accommodate more electronic components on the PCB and enable electronic devices to have smaller PCBs but have more functions, stacked packaging technology has emerged. [0003] The existing package-on-package structure incl...

Claims

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Application Information

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IPC IPC(8): H01L23/31H01L23/498H01L21/56H01L21/60
CPCH01L21/56H01L23/3128H01L23/3135H01L23/49827H01L24/85H01L2224/85007H01L2224/16227H01L2224/32225H01L2224/48247H01L2224/73204H01L2224/73265H01L2924/15192H01L2924/15311H01L2924/19105H01L2224/16225H01L2924/00
Inventor 杨俊
Owner SHUNSIN TECH (ZHONG SHAN) LTD
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