Semiconductor package structure and its manufacturing method
A technology of packaging structure and manufacturing method, which is applied in the direction of semiconductor devices, semiconductor/solid-state device parts, electric solid-state devices, etc., can solve the problems of high cost and thick thickness, and achieve the effect of overall thickness reduction and good heat dissipation effect
Active Publication Date: 2017-09-15
CHIPMOS TECH INC
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- Abstract
- Description
- Claims
- Application Information
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Problems solved by technology
[0003] Take the packaging substrate as an example, most of them have a core layer, so the thickness is thick and the cost is high
Method used
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Embodiment Construction
[0041] Figure 1 to Figure 8 It is a schematic cross-sectional view of the manufacturing process of the semiconductor package structure according to an embodiment of the present invention. Please refer to figure 1 , firstly, a carrier board 10 is provided. In this embodiment, the carrier board 10 can be made of a material with high rigidity, so it is not easy to be bent and deformed by force. Please continue to refer figure 1 , configure the metal sheet 110 on the carrier board 10 . The metal sheet 110 can be directly attached to the carrier 10 through its bottom surface 111 , or temporarily fixed on the carrier 10 through a release adhesive film (not shown) on the bottom surface 111 . The material of the metal sheet 110 can be copper, aluminum, silver or other metal materials with good thermal conductivity.
[0042] Next, please refer to figure 2 For example, chemical vapor deposition (CVD) is used to form a semiconductor oxide (such as silicon dioxide) on the carrier...
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The present invention provides a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a metal sheet, a dielectric layer, a patterned wiring layer, a first chip, and a encapsulated colloid. Dielectric layer coated metal sheet. The dielectric layer has opposing first and second surfaces, at least a first opening on the first surface, and a second opening on the second surface. The metal sheet is located in the second opening and is exposed to the first surface and the second surface, respectively. The patterned line layer is disposed on the second surface. The first chip is disposed on the metal sheet, wherein the first chip is located in the second opening and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface and covers the first chip and the patterned line layer. A method for fabricating a semiconductor package structure is proposed. The semiconductor package structure provided by the invention has a thin overall thickness and has a good heat dissipation effect.
Description
technical field [0001] The invention relates to a packaging structure and a manufacturing method thereof, in particular to a semiconductor packaging structure and a manufacturing method thereof. Background technique [0002] In the semiconductor industry, the production of integrated circuits (ICs) can be mainly divided into three stages: design of integrated circuits, fabrication of integrated circuits, and packaging of integrated circuits. After the integrated circuits of the wafer are manufactured, the active surface of the wafer is provided with a plurality of pads. Finally, the bare chips obtained by dicing the wafer can be electrically connected to the carrier through the pads. Generally speaking, the carrier can be a lead frame, substrate or printed circuit board, and the chip can be bonded by wire bonding or flip chip bonding. The chip is connected to the carrier in such a way that the pads of the chip are electrically connected to the contacts of the carrier, ther...
Claims
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Patent Timeline
Login to View More IPC IPC(8): H01L23/31H01L23/367
CPCH01L23/31H01L23/3107H01L23/367H01L23/3672H01L2224/32245H01L2924/15153H01L2924/15311H01L2224/48227H01L2224/73265H01L2224/16227H01L2924/3511
Inventor 陈宪章
Owner CHIPMOS TECH INC