Ultrasonic digital signal twin-core processing system and method based on FPGA and STM32

Abstract

The invention discloses an ultrasonic digital signal twin-core processing system and method based on an FPGA and an STM32 and belongs to the technical field of ultrasonic sounding. The system comprises a front end circuit, an A / D conversion chip, an FPGA chip and an STM32 chip, the FPGA chip comprises a control unit, a timing sequence generation unit, a serial port transmitter and an FIFO cache unit, and the method can be achieved based on the system. According to the ultrasonic digital signal twin-core processing system and method based on the FPGA and the STM32, the defects of the prior art are overcome. A mode that the FPGA is combined with the STM32 is adopted, the FPGA and the STM32 make good for deficiency, and excessive hardware cables are avoided by using high efficiency, programmable characteristic and other characteristics of the FPGA. The data is processed by using the STM32, peripherals can be operated by using an existing program library, and the system is very convenient to operate.

Description

technical field [0001] The invention specifically relates to a dual-core processing system and method for ultrasonic digital signals based on FPGA and STM32, belonging to the technical field of ultrasonic detection. Background technique [0002] In the receiving system of the ultrasonic digital signal, there are several schemes in the prior art: [0003] (1) Pure single-chip model [0004] This technology uses C08051F340 single-chip microcomputer as the main control chip, and its specific structure is as follows: Figure 2-2 As shown, due to the limited functions of the single-chip microcomputer, a large number of counter chips, latch chips, and SRAM chips are externally connected to this solution. [0005] The main disadvantages of the pure single-chip solution are: [0006] 1. Ordinary single-chip microcomputer pins are limited, about 40 or so, which mainly include clock, power supply, reset, I / O ports, etc. These ports are used to generate data and control lines require...

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Problems solved by technology

[0006] 1. Ordinary single-chip microcomputer pins are limited, about 40 or so, which mainly include clock, power supply, reset, I / O ports, etc. These ports are used to generate data and control lines required to control peripheral devices, and the number often cannot meet Requirements, so it is necessary to add decoding and latch circuits externally to expand the I / O port, the whole system will become very bloated, and the volume of the device will also increase

[0007] 2. The system hardware connection is complicated and the reliability is low

Due to the addition of a large number of discrete components to expand the I / O port, the hardware connection becomes complicated, the interference between signals increases, the reliability is low, and the system power consumption also increases.

[0008] 3. The processing speed is slow. Generally, the processing speed of the single-chip microcomputer is relatively slow, and the resources are limited. It is difficult to realize the human-computer interaction functions such as LCD screen display.

[0012] The design of CPLD / FPGA must follow the real circuit, so it is very troublesome when using CPLD / FPGA to generate computing units. It is necessary to build a large number of hardware computing circuits, which will waste its internal resources, and the implementation of various data processing algorithms is relatively difficult. difficulty

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