Semiconductor process and semiconductor structure

Abstract

The invention provides a semiconductor process and a semiconductor structure. A semiconductor substrate is half cut in the front, then a protective membrane is arranged on the front of the semiconductor substrate, and then the semiconductor substrate is thinned in the back so as to separate each semiconductor unit structure, so that reduced cutting depth prevents a cutting knife from being overused, an active surface of the semiconductor substrate is protected from damage in the process of separating each semiconductor unit, and each semiconductor unit is prevented from deviating in separation. In addition, according to the semiconductor process provided in the invention, the front of the semiconductor substrate is protected by the protective membrane, then plastic packaging and cutting of a plastic packaging material are carried out, so that bad effect of plastic packaging on the front of the semiconductor substrate is prevented; and each of six surfaces of finally formed semiconductor structure has a protective layer, thereby preventing bad effect of external environment on the semiconductor structure, and improving the reliability of the semiconductor structure.

Description

technical field [0001] The invention relates to the technical field of semiconductor design, in particular to a semiconductor process and a semiconductor structure. Background technique [0002] Wafer-level packaging technology is a technology that takes wafers as the processing object, packages many chips on the wafer at the same time, and finally cuts them into individual devices that can be directly mounted on substrates or printed circuit boards. Wafer-level packaging is widely used in mobile and portable electronic products due to its high processing efficiency, low manufacturing cost, and advantages such as lightness, thinness, shortness, and smallness. [0003] figure 1 It is a schematic diagram of a single chip packaging device formed by using the existing wafer packaging technology. It is mainly composed of a bare chip 01, a front protection layer 02, an electrode 03 and a back protection layer 04. The electrode pad 011 on the front of the chip 01 is electrically ...

AI Technical Summary

Problems solved by technology

[0004] Depend on figure 1 It can be seen that the single chip packaged device formed by the existing wafer level packaging process only has a protective layer on the front and back, while the other four sides are exposed, which is easily affected by external forces, thus affecting the reliability of the chip packaged device

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