Three-dimensional memory electromigration test structure and manufacturing method thereof

A technology for testing structures and manufacturing methods, which is applied in semiconductor/solid-state device testing/measurement, circuits, electrical components, etc., and can solve problems such as test result deviation and test structure damage, achieve fast and accurate positioning, achieve precise positioning, and improve manufacturing. the effect of the success rate

Active Publication Date: 2017-11-21
YANGTZE MEMORY TECH CO LTD
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Problems solved by technology

[0005] In view of this, the present invention provides a three-dimensional memory electromigration test structure and its manufacturing method

Method used

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  • Three-dimensional memory electromigration test structure and manufacturing method thereof
  • Three-dimensional memory electromigration test structure and manufacturing method thereof
  • Three-dimensional memory electromigration test structure and manufacturing method thereof

Examples

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[0046] As described in the background art, the test line positioning method in the prior art is likely to cause damage to the test structure, which in turn causes deviations in the test results during the test process.

[0047] Specifically, since the main structure of the test line and the virtual line are the same, there is no major difference, so there is no way to locate the test line through the structural difference, and the test line must be located by setting a mark.

[0048] In the preparation process of the electromigration test structure sample, an oxide layer of tens of nanometers to one hundred nanometers must be reserved on the upper metal wire M02 to avoid the test wire T01 in the M02 from being lost during the preparation of the FIB sample. Observed by SEM (Scanning Electron Microscope, Scanning Electron Microscope) observation depth ( <200nm), the thicker the oxide layer, the less clear the image. In addition, the width of the M2 with 3D NAND double exposure is onl...

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Abstract

The invention provides a three-dimensional memory electromigration test structure and the manufacturing method thereof. In an electromigration test structure manufacturing process, Markers are made on oxide layers of a first virtual line and a second virtual line adjacent to a test line to position the test line. Since markers are made on the oxide layers of the first virtual line and the second virtual line on the two sides of the test line, the metallic line in the middle of markers can be directly positioned as the test line during making an electromigration test structure sample, and rapid and accurate position of the test line can be realized. An electromigration test structure sample can be obtained by cutting the two sides of the test line. Since the markers are on the oxide layers of the first virtual line and the second virtual line, the test line may not be affected, and accurate position of the test line can be realized without damaging the test line and a first metallic line connected with the test line. Sample making success rate is greatly improved, and the positioning time of test line can be shortened.

Description

technical field [0001] The invention relates to the technical field of manufacturing semiconductor devices, in particular to a three-dimensional memory electromigration test structure and a manufacturing method thereof. Background technique [0002] NAND flash memory is a better storage device than hard disk drives, and it has been widely used in electronic products as people pursue non-volatile storage products with low power consumption, light weight and high performance. At present, the planar NAND flash memory is close to the limit of practical expansion. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D NAND memory, that is, 3D NAND, is proposed. [0003] The current 3D NAND M2DP_EM test key (double exposure metal line 2 electromigration test structure) such as figure 1 and figure 2 The design shown, where, figure 1 It is a schematic top view of the three-dimensional memory electromigration test structure; figure 2 It is a...

Claims

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Application Information

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IPC IPC(8): H01L23/544
CPCH01L22/34H01L23/544H01L2223/54433
Inventor 蔚倩倩郭伟仝金雨李桂花李辉
Owner YANGTZE MEMORY TECH CO LTD
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