Multi-site semaphore detection and failure determining system and method

Abstract

The invention discloses a multi-site semaphore detection and failure determining system and method. The system herein implements through an embedded microprocessor and a LCD display module. The embedded microprocessor includes a command processing module, a data storage module, a firmware updating module, an OS detection and repair module, a power voltage control module, an input and output semaphore detection module, a key processing module, a failure processing module, and a handler control module. The system provides necessary means for analyzing and detecting chip DC characteristic indexesby a mass production terminal, integrates a multi-index semaphore set to one system for performing detection and failure determination, comprises detection of chip physical connection characteristics, and greatly increases working efficiency.

Description

technical field [0001] The invention belongs to the technical field of chip detection, and in particular relates to a system and method for chip semaphore detection and failure judgment applied in the mass production stage. Background technique [0002] At present, the existing detection devices are mainly used in the research and development stage. In the mass production stage, there are disadvantages and high investment. The device voltage, current, and pin failure judgment and repair are independent and separate, and multiple failure detections cannot be performed at the same time. They can only be applied to a single chip. For testing, the detection device based on the 8-bit MCU architecture has a single function, few internal integrated peripherals, small program and data storage space, low chip operating frequency, and low data transmission rate, resulting in simple software hierarchical design and low versatility. The development of a new detection and failure judgmen...

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Problems solved by technology

[0002] At present, the existing detection devices are mainly used in the research and development stage. In the mass production stage, there are disadvantages and high investment. The device voltage, current, and pin failure judgment and repair are independent and separate, and multiple failure detections cannot be performed at the same time. They can only be applied to a single chip. For testing, the detection device based on the 8-bit MCU architecture has a single function, few internal integrated peripherals, small program and data storage space, low chip operating frequency, and low data transmission rate, resulting in simple software hierarchical design and low versatility. The development of a new detection and failure judgment device, the external input signal is unstable due to various reasons, resulting in unreliable data, heavy repetitive workload, and the detection equipment does not have a complete detection method for problems caused by the failure of the DC characteristic of the chip and cannot be carried out simultaneously. For power detection and failure analysis, manually taking out the tested chip and burning it brings great time difficulties to the whole test. The test cost is high, and the subsequent maintainability is more difficult; relying on the tester's own skills and carefulness will have a certain impact on the function and performance of the chip test, and in severe cases, the tester will misjudge the problem, increasing the design cost and Testing time; traditional failure analysis methods are restricted by realistic conditions, and can only analyze and judge a single failure item; the development mode of semaphore detection and failure analysis devices is affected by traditional development ideas, lacks composite devices, and cannot be generated automatically The required semaphore can only be manually analyzed separately, which is inefficient and restricts the efficiency of production and testing

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