Fan-out packaging device

Abstract

The invention discloses a fan-out packaging device, which comprises an intermediate board, a packaging substrate and a chip, wherein the intermediate board comprises a substrate and a routing area located at one side of the substrate; a hole is formed in the substrate and comprises a conductive layer; the routing area is electrically connected with one end of the conductive layer in the hole; thepackaging substrate comprises a silicon wafer base layer, a bonding pad and a first rerouting layer; the bonding pad is arranged at one side of the silicon wafer base layer; the first rerouting layeris arranged at the other side of the silicon wafer base layer, wherein the bonding pad is electrically connected with the first rerouting layer; the chip is electrically connected with the routing area of the intermediate board; the packaging substrate is electrically connected with the other end of the conductive layer, so that the chip is electrically connected with the bonding pad of the packaging substrate. According to the fan-out packaging device, the fan-out package accuracy can be improved and the chip is prevented from shifting.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a fan-out packaging device. Background technique [0002] With the development of semiconductor technology, the size of the chip is getting smaller and smaller, and the density of I / O (input / output) pins on the surface of the chip is getting higher and higher. High density I / O pins fan out to low density package pins. [0003] At present, the existing fan-out packaging method includes the following process: providing a carrier board, attaching a layer of double-sided adhesive film on the carrier board, attaching the front side of the chip to the adhesive film, plastic sealing the chip, and peeling off the adhesive film. Film and carrier board, forming rewiring layer, ball planting, and dicing on the front side of the chip. [0004] The inventors of the present invention have found in the long-term research process that the above-mentioned fan-out packaging metho...

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Problems solved by technology

[0004] The inventors of the present invention have found in the long-term research process that the above-mentioned fan-out packaging method directly connects the chip to the packaging substrate, and the node spacing of the packaging substrate is relatively large, which cannot be used for high-precision chips; secondly, in the fan-out packaging method, due to When the plastic film is used, the temperature changes during the plastic sealing of the chip will cause the film to shrink and warp due to the difference in the coefficient of thermal expansion (CTE) of the plastic sealing material, chip and carrier board during plastic sealing, which will cause the chip to shift during plastic sealing. The offset causes difficulties in subsequent processes such as lithography alignment

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