Process for epitaxial growth of silicon in three-dimensional (3D) NAND flash structure

Abstract

The invention provides a process for epitaxial growth of silicon in a three-dimensional (3D) NAND flash structure. The method comprises the steps of depositing a substrate lamination structure; etching the substrate lamination structure to form a channel and a silicon groove in a substrate surface; cleaning the channel and the silicon groove; performing high-temperature annealing; forming epitaxial growth of the silicon, and cleaning the silicon in advance; and performing epitaxial growth of the silicon. By high-temperature annealing, the surface of the silicon groove damaged by etching is oxidized, so that resided polymer in the silicon groove in the bottom of the channel is eliminated, meanwhile, a certain oxidization repair effect also can be generated on the surface, which is damaged,of the silicon subsequently and epitaxially grown, and interface damage and lattice defect are eliminated; the step of wet cleaning is added before high-temperature annealing, the subsequent and better effects of oxidization annealing and interface repair can be obtained; and by the process, the deep channel can be effectively etched, oxide residue is prevented, damage to an interface layer by etching is prevented, so that the epitaxial growth height uniformity of the silicon is improved, an epitaxial growth gap of the silicon is prevented, and the comprehensive performance of a 3D NAND flashis improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a 3D NAND flash memory structure and a manufacturing method thereof, in particular to a silicon epitaxial growth process in a 3D NAND flash memory structure capable of improving the growth quality of a silicon epitaxial layer. Background technique [0002] With the development of planar flash memory, the production process of semiconductors has made great progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limits, existing development technology limits, and storage electron density limits. In this context, in order to solve the difficulties encountered in planar flash memory and to seek lower production costs per unit storage unit, various three-dimensional (3D) flash memory structures have emerged, such as 3D NOR (3D or not) flash memory and 3D NAND (3D NAND) flash memory. [0003] Wherein, in the 3D...

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Problems solved by technology

[0010] However, in the above process, as the number of stacked N / O (Nitride / Oxide) stacking structures in 3D NAND flash memory increases, it becomes more and more difficult to form through etching channels and subsequent cleaning processes in three-dimensional memories. bigger

In order to effectively etch to form a channel, an etch damage layer 7 is often formed at the interface of the etched region (see Figure 1a ), and the interface damage and lattice defects of these etching damage layers will not be repaired in the subsequent pre-cleaning steps, which will further affect the quality of silicon epitaxial growth, such as causing the height of the silicon epitaxial layer to be uneven and vacancies8 (see Figure 1d ) generation

Not only that, but the deep trench also makes it difficult to effectively remove the residual polymer9 at the bottom of the etched trench (see Figure 1a ), which also affects the quality of silicon epitaxial growth

These problems will affect the preparation of the channel and the performance of the final 3D NAND flash memory

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