Method, device, control unit and medium for multilevel power converter

Abstract

The present disclosure relates to a method for reducing low-order harmonics of a multilevel power converter comprising at least one phase leg comprising a plurality of chain-connected cells , each chain-connected cell includes a capacitor. For each phase leg of the converter, the method consists of: obtaining at the current half switching duration (T sw / 2) The current reference voltage used during (u ref ); divide the half-switching duration into multiple time samples; and at the beginning of each time sample (t A , t 1 , t 2 ) ): Based on the obtained current reference voltage, predict the reference voltage waveform in the remainder of the half-switching duration; During the case where a cell is inserted or bypassed in an arm, predict the arm output voltage (U leg ) waveform; and based on the obtained current reference voltage, the predicted reference voltage waveform, and the predicted arm output voltage waveform, predicting the end of the current half-switching duration (t B ) when the flux error (F error ); and based on the predicted flux error, determining whether to insert or bypass the cell during time sampling.

Description

technical field [0001] The present disclosure relates to methods and apparatus for modulating a power converter for reducing low order harmonics. Background technique [0002] A delta-connected multilevel converter, such as a static synchronous compensator (STATCOM), includes an alternating current (AC) side and a direct current (DC) side for each phase leg. The DC bus voltage for the DC side of any phase leg is the sum of the cell capacitor voltages on that particular phase leg. This DC bus voltage is a virtual bus that is not structurally present in the converter. STATCOM consists of three arms, each between two phases. When measuring the virtual DC bus voltage of an arm between phase A and phase B, all cell capacitor voltages in that particular arm are summed together and referred to as the DC bus voltage of phase arm AB. Similarly, in the case of a Y (referred to as Y or star) connected STATCOM, the DC bus voltage is between the phase (A, B or C) and the neutral (refe...

AI Technical Summary

Problems solved by technology

[0006] (i) Fluctuations in the cell capacitor voltage due to instantaneous power flowing through the cell capacitor

[0007] (ii) Improper volt-second balance due to non-idealities, such as variations in the reference voltage over the time period of the carrier signal (i.e., due to low pulse numbers) and variations in the cell capacitor voltage

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