Method for manufacturing semiconductor device
A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, transistors, etc., can solve problems such as high crystal defect density, increased leakage current, and reduced carrier mobility
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Embodiment approach 1
[0032] Figure 1-8 It is a figure which shows the manufacturing method of the semiconductor device concerning Embodiment 1 of this invention. In the method of manufacturing a semiconductor device according to Embodiment 1, first, the structure on the upper surface side of the substrate is formed. figure 1 It shows the state where the structure on the upper surface side of the substrate is formed, and is a cross-sectional view of a semiconductor device in the process of manufacture. The substrate 1 is N-type single crystal silicon. On the upper surface side of the substrate 1, an emitter layer 2 formed of an N+ diffused layer, a base layer 3 formed of a P+ diffused layer, a gate insulating film 4, a gate electrode 5, and metal wirings are formed by a known method. The emitter electrode 6 and so on. In addition, a passivation film may also be formed on these structures.
[0033] Next, the thickness of the substrate 1 is reduced to, for example, about 100 μm by grinding the s...
Embodiment approach 2
[0062] In Embodiment 2 of the present invention, as in Embodiment 1, the buffer layer formed in the buffer layer forming step is activated by the annealing step. The buffer layer after the annealing process has only one maximum point of impurity concentration in the depth direction. Figure 10 It is a graph showing the impurity distribution of the buffer layer 10 according to the second embodiment. shown from Figure 10 Starting from the left side of , the impurity concentration at a position deeper from the lower surface of the substrate moves to the right. The maximum concentrations of the respective implants are connected to form a broad distribution, so that the buffer layer 10 has a gentle impurity profile. As a result, there is one maximum point of the impurity concentration in the buffer layer 10 .
[0063] Figure 10 The impurity distribution of the buffer layer 10 shown in , for example, can be realized by performing ion implantation steps four times and adjusting...
Embodiment approach 3
[0067] Figure 11 It is a cross-sectional view of a semiconductor device formed by the method of manufacturing a semiconductor device according to the third embodiment. Between the collector layer 8 and the buffer layer 10, an intermediate buffer layer 20 implanted with P is formed. Figure 12 is along Figure 11The graph of the impurity distribution of the XII-XII' line in . The peak value of the impurity concentration of the intermediate buffer layer 20 is higher than the peak value of the impurity concentration of the buffer layer 10 .
[0068] In order to manufacture the intermediate buffer layer 20 , first, phosphorus (P) is implanted from the lower surface side of the substrate 1 at an implantation energy of about 500 keV to 8 MeV. This step is called an intermediate buffer layer forming step. Then, an annealing step is performed to activate P. The implantation of P ions may be performed before the buffer layer forming step or after the buffer layer forming step. P...
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