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Parallel FIR decimation filter and design method of parallel FIR decimation filter

A technology for extracting filters and sub-filters, which is applied in the field of communications and can solve problems such as inapplicability of high-speed broadband signals

Active Publication Date: 2018-03-06
INST OF ELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The traditional variable decimation factor filter is realized by the integral comb (Cascade Integrator Comb, CIC) filter, figure 1 Schematic diagram of the structure of a traditional variable decimation factor filter, such as figure 1 As shown, the structure of the traditional variable decimation factor filter is formed by cascading the CIC filter, the compensation decimation filter and the programmable FIR low-pass filter, and the first stage CIC filter passes the processed data to the second stage The second-stage FIR compensation filter, the second-stage FIR compensation filter passes the processed data to the third-stage programmable FIR low-pass filter, and the third-stage programmable FIR low-pass filter outputs the final Processing results to achieve decimation and filtering of high-speed narrowband signals, but CIC filters are suitable for high-speed narrowband signal filtering, and this method is not suitable for high-speed broadband signals

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  • Parallel FIR decimation filter and design method of parallel FIR decimation filter
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  • Parallel FIR decimation filter and design method of parallel FIR decimation filter

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no. 2 example

[0097] In order to better reflect the purpose of the present invention, further illustrations are made on the basis of the first embodiment of the present invention. In the second embodiment, a data processing method of a parallel FIR decimation filter with 3 decimation factors is exemplarily provided, wherein the parallel FIR decimation filter includes 8 parallel inputs, and the decimation factors are 2, 3, 5, the number of taps of the FIR sub-filter is 21 (that is, L=21).

[0098] Figure 4 It is a schematic flow chart of the second embodiment of the data processing method of the parallel FIR decimation filter in the embodiment of the present invention, the method includes:

[0099] Step 401: Determine the number P of parallel operation branches of the parallel FIR decimation filter.

[0100] It should be noted that the parallel FIR decimation filter includes P FIR sub-filters, since one parallel operation branch contains one FIR sub-filter for processing the data in the b...

no. 3 example

[0144] For the method of the embodiment of the present invention, the embodiment of the present invention also provides a parallel FIR decimation filter, the decimation factor of the parallel FIR decimation filter is variable, Figure 7 It is a schematic diagram of the first composition structure of the parallel FIR decimation filter in the embodiment of the present invention, such as Figure 7 As shown, the parallel FIR decimation filter 70 includes: a processor 701 and P FIR sub-filters 702, where P takes a positive integer, wherein,

[0145] The processor 701 is used to perform the following steps: cache M paths of parallel input data acquired at the current moment, M is an integer greater than P; combine all the cached data to obtain multiple data groups; extract data from multiple data groups according to the current extraction factor P data groups are extracted from the group; the P data groups are respectively output to P FIR sub-filters to perform data processing opera...

no. 4 example

[0163] In order to better reflect the purpose of the present invention, further illustrations will be made on the basis of the third embodiment of the present invention. Figure 8 It is a schematic diagram of the second composition structure of the parallel FIR decimation filter in the embodiment of the present invention, as Figure 8 As shown, the parallel FIR decimation filter includes: a data cache unit 81, a data combination unit 82, an extraction unit 83 and a filtering unit 84; wherein,

[0164] The data cache unit 81 is used to cache the M parallel input data obtained at the current moment, and M is 8 in this embodiment;

[0165] A data combination unit 82, configured to combine all the cached data to obtain multiple data groups;

[0166] The extraction unit 83 is used to extract P data groups from multiple data groups according to the current extraction factor, and output the P data groups to the FIR sub-filter in the corresponding parallel operation branch;

[0167]...

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Abstract

The embodiment of the invention discloses a data processing method of a parallel FIR decimation filter. A decimation factor of the parallel FIR decimation filter is variable; the parallel FIR decimation filter comprises P FIR sub-filters, and P is positive integer; the data processing method of the parallel FIR decimation filter comprises the following steps: caching M paths of parallel input dataacquired at the current moment, wherein M is the integer greater than P; acquiring multiple data sets by combining all cached data; decimating P data sets from multiple data sets according to the current decimation factor; and respectively outputting P data sets to P FIR sub-filters so as to execute the data processing operation. The embodiment of the invention further discloses a parallel FIR decimation filter.

Description

technical field [0001] The invention relates to the field of communication technology, in particular to a data processing method of a parallel FIR decimation filter and a parallel FIR decimation filter. Background technique [0002] The finite impulse response (Finite Impulse Response, FIR) digital filter is the most important device in the digital signal processing system, and has been widely used in many fields, such as wireless communication, remote sensing satellite receiver and radio telescope receiving equipment, etc. . In recent years, with the continuous development of modern digital signal processing technology, there are more and more types of signals to be processed, and the situation is becoming more and more complicated. The requirements for the processing speed of digital signal processing systems are also increasing. In order to further increase the speed of digital signal processing, parallel processing technology has been more and more widely used in digita...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03H17/00H03H17/02
CPCH03H17/0063H03H17/0223H03H2017/0081
Inventor 马瑜杰杜江曲春辉肖灯军
Owner INST OF ELECTRONICS CHINESE ACAD OF SCI