Fabrication method of semiconductor structure

Abstract

A method for manufacturing a semiconductor structure, comprising: providing a substrate and discrete fins on the substrate; the extending direction of the fins is a first direction, and the direction perpendicular to the first direction is a second direction; a substrate between the fins An initial isolation layer is formed on the top, including a first initial isolation layer for realizing the isolation of the fins in the first direction; a part of the thickness of the first initial isolation layer is removed to form a first isolation layer, so that the top of the first isolation layer is lower than the top of the fin, Forming trenches between the fins; forming a second isolation layer filling the trenches; forming protective sidewalls on the sidewalls of the second isolation layer higher than the top of the fins; removing part of the thickness of the second initial isolation layer and the second isolation Floor. In the present invention, protective sidewalls are formed on the sidewalls of the second isolation layer higher than the top of the fins, and when a part of the thickness of the second isolation layer is removed, the protective sidewalls play a protective role on the sidewalls of the second isolation layer to avoid the second isolation layer. The problem of raised defects on the top due to insufficient lateral etching.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a method for manufacturing a semiconductor structure. Background technique [0002] With the continuous development of semiconductor process technology, the development trend of semiconductor process nodes following Moore's Law continues to decrease. In order to adapt to the reduction of the process node, the channel length of the MOSFET field effect tube has to be shortened. The shortening of the channel length has the advantages of increasing the die density of the chip and increasing the switching speed of the MOSFET field effect tube. [0003] However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control ability of the gate to the channel becomes worse, resulting in the phenomenon of subthreshold leakage, namely So-called short-channel effects (SCE: short-channel effects) are more l...

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Problems solved by technology

[0006] However, even with the introduction of stress layers in the FinFET fabrication process, the electrical performance of state-of-the-art semiconductor devices is still poor

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