Process integration method for improving flash memory unit

Abstract

The invention provides a process integration method for improving a flash memory unit. The method comprises steps that a substrate structure is formed through device ion implantation; a flash memory oxide layer, a floating gate polysilicon layer and a silicon nitride layer are sequentially deposited; a shallow trench isolation structure is formed, and a silicon oxide layer is deposited on the shallow trench isolation structure; pre-cleaning processing is carried out, the silicon nitride layer and the silicon oxide layer of the shallow trench isolation structure are partially removed through etching to expose a floating gate polysilicon tip; the exposed floating gate polysilicon tip is oxidized to round the tip; etching processing is carried out, the silicon oxide layer of the shallow trench isolation structure is partially removed, and the silicon oxide for rounding the floating gate polysilicon tip is further removed; the silicon nitride layer is removed through etching till the floating gate polysilicon layer is exposed. The method is advantaged in that arcing of the floating gate tip is realized in advance through the added silicon oxide, arcing of the floating gate tip and thenon-damaged flash memory unit at the top portion of the floating gate are realized, and another optimization method is provided for continuously reducing the flash memory unit.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a process integration method for improving a flash memory unit. Background technique [0002] Flash memory has been widely used as the best choice for non-volatile memory applications due to its advantages of high density, low price, and electrical programmability and erasability. At present, flash memory cells are mainly implemented at the 65nm technology node. With the demand for large-capacity flash memory, the number of chips on each silicon wafer will be reduced by using the existing technology nodes. At the same time, the increasing maturity of new technology nodes also promotes the production of flash memory cells with high-node technologies. It means that the size of the flash memory unit needs to be reduced. The reduction of the active area width and channel length of the flash memory unit according to the original structure will affect ...

AI Technical Summary

Problems solved by technology

[0005] Disadvantages: After the removal of silicon nitride, the flash memory area is opened to remove silicon oxide, which affects the surface of the floating gate, and the uniformity of the surface oxidation becomes worse after removal

[0008] Disadvantages: The sharp corners of the floating gate cannot be exposed because the silicon nitride has not been removed, resulting in the sharp corners of the floating gate not being rounded, and the subsequent high electric field is easy to accumulate, and there is a risk of charge loss

[0009] These two methods cannot simultaneously realize the rounding of the corners of the floating gate and the problem that the top of the floating gate of the flash memory is damaged by dry etching

Images