A process integration method for improving flash memory cells

Abstract

The invention proposes a method for improving the process integration of flash memory cells, including: device ion implantation to form a substrate structure; sequentially depositing a flash memory oxide layer, a floating gate polysilicon layer and a silicon nitride layer; forming a shallow trench isolation structure and depositing an oxide layer therein. Silicon layer: perform pre-cleaning treatment, etch to remove part of the silicon nitride layer and part of the silicon oxide layer in the shallow trench isolation structure, exposing the floating gate polysilicon sharp corner; oxidize the exposed floating gate polysilicon sharp corner to make the sharp corner smooth Carry out etching treatment to remove part of the silicon oxide layer in the shallow trench isolation structure, and simultaneously remove the silicon oxide used for rounding the corners of the floating gate polysilicon; etch and remove the silicon nitride layer until the floating gate polysilicon is exposed layer. The present invention utilizes the increased silicon oxide to advance the rounding of the sharp corners of the floating gates, and at the same time realizes the rounding of the sharp corners of the floating gates and the undamaged flash memory cells on the top of the floating gates of the flash memory cells, so as to provide continuous shrinkage of flash memory Cells provide another way to optimize.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a process integration method for improving a flash memory unit. Background technique [0002] Flash memory has been widely used as the best choice for non-volatile memory applications due to its advantages of high density, low price, and electrical programmability and erasability. At present, flash memory cells are mainly implemented at the 65nm technology node. With the demand for large-capacity flash memory, the number of chips on each silicon wafer will be reduced by using the existing technology nodes. At the same time, the increasing maturity of new technology nodes also promotes the production of flash memory cells with high-node technologies. It means that the size of the flash memory unit needs to be reduced. The reduction of the active area width and channel length of the flash memory unit according to the original structure will affect ...

AI Technical Summary

Problems solved by technology

[0005] Disadvantages: After the removal of silicon nitride, the flash memory area is opened to remove silicon oxide, which affects the surface of the floating gate, and the uniformity of the surface oxidation becomes worse after removal

[0008] Disadvantages: The sharp corners of the floating gate cannot be exposed because the silicon nitride has not been removed, resulting in the sharp corners of the floating gate not being rounded, and the subsequent high electric field is easy to accumulate, and there is a risk of charge loss

[0009] These two methods cannot simultaneously realize the rounding of the corners of the floating gate and the problem that the top of the floating gate of the flash memory is damaged by dry etching

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