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Single wafer real-time etch rate and uniformity predictor for plasma etch process

A plasma and etching rate technology, applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device testing/measurement, discharge tubes, etc., and can solve problems such as changes in chamber conditions

Active Publication Date: 2019-12-27
MICROCHIP TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, differences between various processes and / or wafer loading types can cause variations in chamber conditions

Method used

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  • Single wafer real-time etch rate and uniformity predictor for plasma etch process
  • Single wafer real-time etch rate and uniformity predictor for plasma etch process
  • Single wafer real-time etch rate and uniformity predictor for plasma etch process

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Embodiment Construction

[0027] The teachings of the present invention can provide methods for real-time verification of etch rate and uniformity with respect to plasma etch chambers using single wafer runs. The processes taught herein can reduce and / or eliminate waste / runaway material caused by changes in etch chamber conditions.

[0028] A typical qualification run employed between varying plasma etch processes can take more than thirty minutes to complete. In many cases, the time is largely determined by the time required to measure and verify the data after the etch run is complete, often using separate metrology equipment. For example, laser interferometers and CCD arrays are expensive and difficult to integrate with existing plasma etch process tools.

[0029] The example procedures herein can be used to test and confirm etch rate and uniformity without these time consuming measurement steps. The example process, and others incorporating the teachings of this disclosure, may provide an efficie...

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PUM

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Abstract

The present invention involves semiconductor manufacturing, especially a real -time method for the etching rate for authentication of plasma etching. A method for testing the semiconductor plasma etching cavity can include: the membrane is deposited on the substrate of the chip, the chip contains the central and edge area; Regional isolation patterns deposit photosynthesis on the top of the membrane; and the etching process of the chip execution contains at least three processes steps. The three processes steps can include: the membrane is etched in any region that is not covered by optical resistance, until the first clear end point signal is implemented; And the diaphragm is etched in any area exposed by the removal of the retractor of the light to the second clear endpoint. The description can further determine whether the two endpoints are implemented within the corresponding setting before the corresponding setting, and if the two endpoints are implemented within the previously set up tolerance, then the se iccup etching cavity chamber is certified as a verification verification. Essence

Description

[0001] Cross References to Related Applications [0002] This application claims priority to commonly-owned US Provisional Patent Application No. 62 / 208,295, filed August 21, 2015, which is hereby incorporated by reference herein for all purposes. technical field [0003] The present invention relates to semiconductor manufacturing, and more particularly to a real-time method for qualifying the etch rate of a plasma etch process. Background technique [0004] One way to make semiconductor processing facilities more efficient involves combining multiple wafer processes to run in a single plasma chamber. However, differences between various processes and / or wafer loading types can cause chamber conditions to vary. Plasma etching is commonly used to process integrated circuits and involves bombarding a sample with pulses of a high velocity plasma discharge. In each case, the gaseous etch chemistry forms volatile compounds in which the material is etched. Running multiple pr...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01J37/32
CPCH01J37/32935H01J37/32963H01J2237/334H01J2237/3343H01L21/02164H01L21/0274H01L21/3065H01L21/3081H01L22/12
Inventor 贾斯丁·希罗奇·萨托B·D·亨尼斯Y·C·基梅尔
Owner MICROCHIP TECH INC