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Link-layer verification platform and method of using binary to save excitation and simulation results

A verification platform and verification method technology, applied in the direction of design optimization/simulation, special data processing applications, instruments, etc., can solve the problems of different results, low verification efficiency, and a large number of test incentive contents, so as to simplify the operation and improve the verification effect. Effect

Inactive Publication Date: 2018-04-20
ZHENGZHOU YUNHAI INFORMATION TECH CO LTD
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  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In the above-mentioned prior art, usually because the link layer protocol may be more complicated, and there are many types of test message data structures, the amount of test stimulus content is huge, and the output results may be different due to different configurations of the design to be tested. It is difficult to check the results
The usual method is to write the expected results in the result checking module to compare with them, or to view the results through the simulation waveform, and the verification efficiency is low

Method used

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  • Link-layer verification platform and method of using binary to save excitation and simulation results
  • Link-layer verification platform and method of using binary to save excitation and simulation results

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Embodiment 1

[0037] This embodiment proposes a link layer verification platform that uses binary storage for incentives and simulation results. The verification platform (Testbench) is written in Verilog language, as shown in the attached figure 2 As shown, its structure includes:

[0038] The message generation module Frame_Gen is used to generate test stimulus messages;

[0039] Specifically, the message generation module contains a TXT_GEN module, which is used to save the stimulus file as a binary file, and use the generated binary file to verify the link layer function of the chip; binary is the most common file format, mainly storing text Information, that is, text information; most operating systems today use Notepad and other programs to save, and most software can view it, such as Notepad, browsers, etc.;

[0040] The TXT_GEN module saves Data_gen.v (original file) and Data_exp.v (expected file); Data_gen.v is used to save the original message generated by the message, and Data_...

Embodiment 2

[0053] The link layer verification platform using binary storage of incentives and simulation results proposed in this embodiment, on the basis of the link layer verification platform in Example 1, takes the design under test as a link layer interface module of the QPI protocol, and provides a For specific implementation, learn more about the technical solutions and technical advantages of the link layer verification platform.

[0054] Described design DUT to be tested adopts the link layer interface module of QPI agreement, is used for processing incentive message, realizes utilizing the link layer function of binary file verification QPI agreement; QPI: the QuickPath Interconnect of Intel, is translated as fast channel interconnection; In fact, its official name is CSI, Common System Interface, which is used to realize direct interconnection between chips.

[0055] Since the link layer interface module usually has multiple channels, and each channel is distinguished by a spe...

Embodiment 3

[0067] The link layer verification platform that uses binary storage of incentives and simulation results proposed in this embodiment, on the basis of the link layer verification platform in Embodiment 2, uses the message generation module Frame_Gen according to the link layer data format of the QPI protocol to generate multiple Taking a Flit message as an example, to further introduce the technical solution and technical advantages of the QPI protocol link layer verification platform in detail.

[0068] The message generation module Frame_Gen generates various Flit messages (for example, six types of Flit messages, specifically HOM, SNP, NDR, DRS, NCB, and NCS) according to the link layer data format of the QPI protocol. While generating the above-mentioned various Flit messages, generate the Data_gen.v file in order to record the production of the messages; according to the above-mentioned various Flit messages after the processing and expectations of the CUT to be tested, wr...

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Abstract

The invention discloses a link-layer verification platform of using binary to save excitation and simulation results, and relates to chip verification technology. The platform includes: a message generation module, which is used for generating a test excitation message, wherein an excitation file is saved as a binary file through a TXT_GEN module thereof, Data_gen.V is set to save an original message generated by the message, and Data_exp.V is set to save a desired result message; a to-be-tested design, which is used for processing the excitation message; and a message checking module, which is used for receiving a result message output by the to-be-tested design, wherein the result message is saved as a binary file of Data_rcv.V through a TXT_GEN module thereof, and the files of Data_exp.v and Data_rcv.v are compared to complete chip link-layer verification. According to the platform, operations of verifying chip link-layer functions are greatly simplified, and a verification effect is improved. The invention also discloses a link-layer verification method of using the binary to save the excitation and simulation results.

Description

technical field [0001] The invention relates to chip verification technology, in particular to a link layer verification platform and method using binary storage for incentives and simulation results. Background technique [0002] In the field of IC / FPGA design, as the design scale continues to increase, the time taken for simulation verification becomes longer and longer. Usually, a test platform (Testbench) will be built for the design to be tested. The test platform is a piece of simulation code, often written in languages ​​such as Verilog, VHDL, and SystemC. [0003] The existing common verification platform structure, as attached figure 1 As shown, the existing test platform (Testbench), usually as shown in the figure, uses the code to write the message generation module (Frame_Gen) to generate test incentives, obtain the test results after passing the design under test (DUT), and output the results to the message inspection Module (Frame_Chk), which checks the corr...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F30/20G06F30/398
Inventor 符云越
Owner ZHENGZHOU YUNHAI INFORMATION TECH CO LTD
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