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Adaptive dead-time control circuit for DC-DC converter

A dead-time control and control circuit technology, applied in the field of microelectronics, can solve the problem of reducing converter efficiency due to dead time, and achieve the effects of improving overall conversion efficiency, avoiding loss of efficiency, and reducing power loss

Active Publication Date: 2018-05-04
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This excessive dead time reduces the efficiency of the converter

Method used

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  • Adaptive dead-time control circuit for DC-DC converter
  • Adaptive dead-time control circuit for DC-DC converter
  • Adaptive dead-time control circuit for DC-DC converter

Examples

Experimental program
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Embodiment 1

[0051] See figure 1 , figure 1 A schematic structural diagram of an adaptive dead-time control circuit for a DC-DC converter provided by an embodiment of the present invention. The control circuit 10 includes:

[0052] The detection sub-circuit 11 is used to generate a control signal according to the voltage of the terminal to be detected in the sub-circuit to be controlled;

[0053] The delay sub-circuit 12 is electrically connected to the detection sub-circuit 11, and is used to generate a non-overlapping clock signal adaptive to the dead time of the power transistor in the sub-circuit to be controlled according to the control signal and the modulation signal.

[0054] Further, see figure 2 , figure 2 It is a schematic structural diagram of a detection sub-circuit provided by an embodiment of the present invention. The detection sub-circuit 11 includes: a D flip-flop D_TRIGER, a first inverter INV1, a second inverter INV2, a third inverter INV3, a first resistor R1, a...

Embodiment 2

[0083] The principle and implementation of the present invention will be described in detail below in combination with specific application circuits.

[0084] Specifically, see Figure 6 , Figure 6 A schematic diagram of a local circuit structure of a DC-DC converter provided by an embodiment of the present invention; in this circuit structure, it includes the detection sub-circuit and the delay sub-circuit as described in Embodiment 1, and also includes the sub-circuit to be controlled and logic controllers;

[0085] Specifically, the sub-circuit to be controlled includes: an inductor L, a fourth PMOS transistor PM4, a third NMOS transistor NM3, a first driver DRIVE1, a second driver DRIVE2, a fourth capacitor C4, a fourth resistor R4, a fifth resistor R5 and a load Resistance Rout; where,

[0086] The inductance L, the fourth PMOS transistor PM4 and the load resistor Rout are sequentially connected in series between the input voltage terminal Vin and the ground terminal ...

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Abstract

The invention relates to an adaptive dead-time control circuit for a DC-DC converter. The control circuit 10 comprises a detection sub-circuit 11 and a delay sub-circuit 12, wherein the detection sub-circuit 11 is used for generating control signals according to voltage of a to-be-detected end in a to-be-controlled sub-circuit; the delay sub-circuit 12 is electrically connected with the detectionsub-circuit 11 and used for generating non-overlapping clock signals adaptive to dead-time of a power tube in the to-be-controlled sub-circuit according to the control signals and modulation signals.With adoption of the adaptive dead-time control circuit for the DC-DC converter, adaptive regulation of the dead-time can be realized according to different load currents and different input voltages,so that efficiency loss caused by too short dead-time of the DC-DC converter is avoided, power consumption loss caused by excessive dead-time in the DC-DC converter is reduced, and overall conversionefficiency of the DC-DC converter is increased.

Description

technical field [0001] The invention belongs to the technical field of microelectronics, in particular to an adaptive dead-time control circuit for a DC-DC converter. Background technique [0002] The turn-on and cut-off of the power transistor in the DC-DC converter has non-ideal effects during the conversion process, and there is a state that the PMOS transistor and the NMOS transistor are turned on at the same time. In this state, there is a path between the power supply and the ground, resulting in a large energy loss and reducing the conversion efficiency of the converter. Therefore, we introduce a dead time to prevent the PMOS transistor and the NMOS transistor from being turned on at the same time. At the same time, too long or too short dead time will affect the conversion efficiency of the entire converter. [0003] Traditional converters use a fixed dead time, and in order that the PMOS transistor and the NMOS transistor will not be turned on at the same time und...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H02M3/158
CPCH02M3/158
Inventor 刘帘曦陈成廖栩峰朱樟明杨银堂
Owner XIDIAN UNIV
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