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FPGA-based data flow control module, control method and circuit
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A technology of control modules and control methods, which is applied in the direction of program control, program control, and electrical program control in sequence/logic controllers, which can solve the problems of master-slave communication failure and achieve the goal of reducing power consumption and improving utilization Effect
Inactive Publication Date: 2018-06-29
ZHENGZHOU YUNHAI INFORMATION TECH CO LTD
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Problems solved by technology
[0005] The present invention solves the technical problem that conventional peripheral interfaces such as SPI, UART, and IIC cannot communicate with master and slave, and are prone to blockage or idle state
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Embodiment 1
[0028] like figure 1 As shown, a data flow control module based on FPGA includes:
[0029] The peripheral device bus interface Apb_interface is used to transmit APB bus signals and obtain dev status signals;
[0030] The RAM module, including areas dev0, dev1, ..., is used to map the state information of devices dev0, dev1, ... respectively;
[0031] The RAM controller module is used to classify device data and store them in areas in the random access memory respectively.
[0032] The Reconfig ms_dev module (Master reconfig module) is used to improve the data transmission rate of the slave connected to the FPGA-based data flow control module when the transmission state in the device in the random access memory changes too quickly.
[0033] The Fc gating logic for sl_dev module (Fc gating logic module) is used to transmit the signals of slave devices ae, id, and af, and notify the slave end connected to the FPGA-based data flow control module to change the receiving or sendin...
Embodiment 2
[0035] like figure 2 As shown, the application circuit of the FPGA-based data flow control module includes the FPGA-based data flow control module FC master interconnected through the APB / AXI / AHB bus, the SPI interface master device SPI 0master, UART0, and through the APB / AXI / AHB bus AHB bus interconnected flow control slave device FC slave, SPI interface slave device SPI 0slave, UART1, data flow control module FC master also communicates with flow control slave device FC slave through ae_m, id_m, af_m, ae_s, id_s, af_s signals. SPI 0master is connected with SPI 0slave. UART devices are connected to each other.
[0037] Divide the RAM area, map the status information of dev0, dev1, dev2, and dev3 respectively, read the identity and status information of the slave devices SPI 0master, UART0, SPI 0slave, and UART1 connected to the data flow control mod...
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Abstract
The embodiment of the invention discloses an FPGA-based data flow control module, a control method and a circuit and belongs to the field of chip design. The FPGA-based data flow control module includes a peripheral device bus interface, a random access memory, a random accessmemory controller, a main port reconfiguration module and a flow control gate logic module. The control method includes the steps of reading identity and state information of a slave device linked to the data flow control module, and mapping the identity and state information in a corresponding area in the random accessmemory; determining whether or not a data jam of the slave device occurs according to the internally read status information of the slave device or determining whether or not data of the slave deviceis about to overflow or idle according to a transmitted slave device signal, and correspondingly changing the transmission rate according to needs. The problem that a peripheral interface end is blocked or is in an idle state is solved, and the utilization of a peripheralbus is effectively increased. The FPGA-based data flow control module, the control method and the circuit have the advantages of adjusting the transmission rate and reducing the power consumption according to actual transmission situations.
Description
technical field [0001] The invention relates to the field of chip design, in particular to the general data flow control design of the data communication interface in the process of data transmission between hardware. Background technique [0002] Since FPGA has the advantages of fast speed, high efficiency, flexibility and stability, and high integration, it is very necessary in hardware logic verification and design. In serial communication, because there are generally only data lines and clock lines on the serial bus, data packets are often classified between serial ports to achieve the exchange of master-slave configuration information. Therefore, adding a flow control logic module to serial communication can speed up master-slave device communication and prevent data congestion or idle state. On the basis of discussing the logic principle, the hardware implementation principle is proposed, and the data flow control logic is realized with Verilog hardware description la...
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